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w WM5102 audio hub codec with voice processor dsp wolfson microelectronics plc production data, may 2013, rev 4.0 [1] this product is protected by patents us 7,622,984, us 7,626,445, us 7,765,019 and gb 2,432,765 copyright ? 2013 wolfson microelectronics plc description the WM5102 [1] is a highly-integrated low-power audio system for smartphones, tablets and other portable audio devices. it combines wideband telephony voice processing with a flexible, high-performance audio hub codec. the WM5102 digital core provides a powerful combination of fixed-function signal processing blocks with a programmable dsp. these are supported by a fully-flexible, all-digital audio mixing and routing engine with sample rate converters, for wide use-case flexibility. the programmable dsp is optimised for wolfson?s wideband voice processing which includes multi-mic noise reduction and echo cancellation. many other audio algorithms can also be implemented. fixed-functi on signal processing blocks include filters, eq, dynamics processors and sample rate converters. a slimbus interface supports multi-channel audio paths and host control register access. multiple sample rates are supported concurrently via the slimbus interface. three further digital audio interfaces are provided, each supporting a wide range of standard audio sample rates and serial interface formats. automatic sample rate detection enables seamless wideband/narrowband voice call handover. two stereo headphone drivers each provide stereo ground- referenced or mono btl outputs, with noise levels as low as 2.3 v rms for hi-fi quality line or headphone output. the codec also features stereo 2w class-d speaker outputs, a dedicated btl earpiece output and pdm for external speaker amplifiers. a signal generator for controlling haptics devices is included; vibe actuat ors can connect directly to the class-d speaker output, or via an external driver on the pdm output interface. all inputs, outputs and system interfaces can function concurrently. the WM5102 supports up to six microphone inputs, each either analogue or pdm digital. microphone activity detection with interrupt is available. a smart accessory interface supports most standard 3.5mm accessories. impedance sensing and measur ement is provided for external accessory and push-button detection. the WM5102 power, clocking and output driver architectures are all designed to maximise battery life in voice, music and standby modes. low-power ?sleep? is supported, with configurable wake-up events. the WM5102 is powered from a 1.8v external supply. a separate supply is required for the class d speaker drivers (typically direct connection to 4.2v battery). two integrated flls provide support for a wide range of system clock frequencies. the WM5102 is configured using the i2c, spi or slimbus interfaces. the fully-differential internal analogue architecture, minimal analogue signal paths and on-chip rf noise filters ensure a very high degree of noise immunity. features ? audio hub codec with integrated voice processor dsp ? programmable audio effects and voice processing functions - transmit-path noise reduc tion and echo cancellation - receive-path enhancement and noise reduction - wind noise, sidetone and other programmable filters - dynamic range control, fully parametric eqs ? multi-channel asynchronous sample rate conversion ? integrated 6/7 channel 24-bit hi-fi audio hub codec - 6 adcs, 96db snr mi crophone input (48khz) - 7 dacs, 113db snr headphone playback (48khz) ? audio inputs - up to 6 analogue or digital microphone inputs - single-ended or differential mic/line inputs ? multi-purpose headphone / earpiece / line output drivers - 2 stereo output paths - 29mw into 32 ? load at 0.1% thd+n - 100mw into 32 ? btl load at 5% thd+n - 6.5mw typical headphone playback power consumption - pop suppression functions - 2.3v rms noise floor (a-weighted) ? mono btl earpiece output driver ? 2 x 2w stereo class d speaker output drivers - direct drive of external haptics vibe actuators ? two-channel digital s peaker (pdm) interface ? slimbus? audio and control interface ? 3 full digital audio interfaces - standard sample rates from 4khz up to 192khz - ultrasonic accessory function support - tdm support on all aifs - 8 channel input and output on aif1 ? flexible clocking, derived from mclkn, bclkn or slimbus ? 2 low-power flls support reference clocks down to 32khz ? advanced accessory detection functions - low-power standby mode and configurable wake-up ? configurable functions on 5 gpio pins ? integrated ldo regulators and charge pumps ? support for single 1.8v supply operation ? small w-csp package, 0.4mm pitch applications ? smartphones and multimedia handsets ? tablets and mobile internet devices (mid) ? general-purpose low-power audio codec hub
WM5102 production data w pd, may 2013, rev 4.0 2 block diagram digital core multi-mic tx noise reduction acoustic echo cancellation rx automatic volume control 5-band equaliser (eq) dynamic range control (drc) low pass / high pass filter (lhpf) asynchronous sample rate conversion automatic sample rate detection programmable dsp tone generator noise generator pwm signal generator haptic control signal generator digital audio interface aif1 aif1txdat aif1rxdat aif1bclk aif1lrclk digital audio interface aif2 aif2txdat aif2rxdat aif2bclk aif2lrclk digital audio interface aif3 aif3txdat aif3rxdat aif3bclk aif3lrclk + - adc + - adc digital mic interface + - adc + - adc digital mic interface + - adc + - adc digital mic interface in1ln/dmicclk1 in1lp in1rn/dmicdat1 in1rp in2ln/dmicclk2 in2lp in2rn/dmicdat2 in2rp in3ln/dmicclk3 in3lp in3rn/dmicclk3 in3rp spkoutlp spkoutln spkoutrp spkoutrn dac dac spkclk spkdat dac hpout2l hpout2r dac dac hpout1l hpout1r dac dac hpout1fb1/micdet2 micdet1/hpout1fb2 hpout2fb hpdetl hpdetr external accessory detect spkgndr spkvddr spkgndl spkvddl micbias generators charge pump 2 charge pump 1 ldo 2 micbias1 micbias2 cp2ca cp2cb cp1ca cp1cb cp1voutp cp1voutn micbias3 cpvdd cpgnd cp2vout micvdd ldo 1 ldoena ldovdd ldovout dbvdd1 dgnd jtag test access tms tdo tdi tck trst dbvdd2 dbvdd3 dcvdd reference generator avdd agnd vrefc pdm driver epoutp epoutn slim bus interface slimclk slimdat gpio1 gpio2 gpio3 gpio4 gpio5 gpio jackdet reset irq cif2mosi cif2miso cif2sclk cif2ss cif1addr cif1sclk cif1sda control interface aifnbclk aifnlrclk slimclk mclk2 mclk1 sysclk clocking control 2 x fll asyncclk aec (echo cancellation) loopback
production data WM5102 w pd, may 2013, rev 4.0 3 table of contents descript ion ................................................................................................................ 1 ? featur es ..................................................................................................................... 1 ? applications .............................................................................................................. 1 ? block diag ram ......................................................................................................... 2 ? table of co ntents .................................................................................................. 3 ? pin config uration ................................................................................................... 7 ? ordering info rmation ........................................................................................... 7 ? pin descri ption ......................................................................................................... 8 ? absolute maximu m ratings ............................................................................... 13 ? recommended operatin g condit ions ............................................................ 14 ? electrical charact eristics ............................................................................ 15 ? terminology ................................................................................................................... .... 26 ? typical perfo rmance .......................................................................................... 27 ? typical power co nsumption ........................................................................................ 27 ? typical signal latency ................................................................................................... 28 ? signal timing re quiremen ts ............................................................................. 29 ? system clock & frequency locked loop (fll) ...................................................... 29 ? audio interface timing ................................................................................................... 31 ? digital microphone (dmic) interface timing .................................................................................... ............................ 31 ? digital speaker (pdm) interface timing ........................................................................................ ................................. 32 ? digital audio interface - master mode ......................................................................................... ................................ 33 ? digital audio interface - slave mode .......................................................................................... ................................... 34 ? digital audio interface - tdm mode ............................................................................................ .................................... 35 ? control interface timing ............................................................................................. 36 ? 2-wire (i2c) co ntrol mode ..................................................................................................... .............................................. 36 ? 4-wire (spi) control mode ..................................................................................................... .............................................. 37 ? slimbus interface timing ............................................................................................... 38 ? device des cription ............................................................................................... 39 ? introduction .................................................................................................................. .... 39 ? hi-fi audio codec ............................................................................................................. ........................................................ 39 ? digital audio core ............................................................................................................ ..................................................... 40 ? digital interfaces ............................................................................................................ ..................................................... 40 ? other features ................................................................................................................ ...................................................... 41 ? input signal path ............................................................................................................. . 42 ? analogue microphone input ..................................................................................................... ........................................ 43 ? analogue line input ........................................................................................................... ................................................... 43 ? digital microphone input ...................................................................................................... ............................................. 44 ? input signal path enable ...................................................................................................... .............................................. 45 ? input signal path sample rate control ......................................................................................... .............................. 46 ? input signal path configuration ............................................................................................... ..................................... 47 ? input signal path digital volume control ...................................................................................... ............................ 50 ? digital microphone interface pull-down ........................................................................................ ........................... 55 ? digital core .................................................................................................................. ...... 56 ? digital core mixers ........................................................................................................... .................................................... 58 ? digital core inputs ........................................................................................................... .................................................... 61 ? digital core output mixers .................................................................................................... ........................................... 62 ? mic mute mixer ................................................................................................................ ......................................................... 65 ? 5-band parametric equaliser (eq) .............................................................................................. ..................................... 66 ? dynamic range control (drc) ................................................................................................... ........................................ 71 ? low pass / high pass digital filter (lhpf) .................................................................................... ................................. 81 ? digital core dsp .............................................................................................................. ....................................................... 84 ?
WM5102 production data w pd, may 2013, rev 4.0 4 tone generator ................................................................................................................ ..................................................... 85 ? noise generator ............................................................................................................... ..................................................... 87 ? haptic signal generator ....................................................................................................... ............................................. 87 ? pwm generator ................................................................................................................. ..................................................... 91 ? sample rate control ........................................................................................................... ................................................ 93 ? asynchronous sample rate converter (asrc) ..................................................................................... .................. 101 ? isochronous sample rate converter (isrc) ...................................................................................... ...................... 104 ? dsp firmware control ................................................................................................. 108 ? dsp firmware memory control ................................................................................................... .................................. 108 ? dsp firmware execution ........................................................................................................ ........................................... 110 ? digital audio interface ................................................................................................ 111 ? master and slave mode operation ............................................................................................... ................................ 112 ? audio data formats ............................................................................................................ ................................................ 112 ? aif timeslot configuration .................................................................................................... ......................................... 114 ? tdm operation between t hree or more devices ................................................................................... ................. 116 ? digital audio inte rface control ............................................................................. 118 ? aif sample rate control ............................................................................................................................... .................... 118 ? aif master / slave control .................................................................................................... .......................................... 118 ? aif signal path enable ........................................................................................................ ............................................... 121 ? aif bclk and lrclk control .................................................................................................... ......................................... 124 ? aif digital audio data control ................................................................................................ ....................................... 128 ? aif tdm and tri-state control ................................................................................................. ....................................... 131 ? aif digital pull-up and pull-down ............................................................................................. .................................... 132 ? slimbus interface .......................................................................................................... 13 4 ? slimbus device parameters ..................................................................................................... ........................................ 134 ? slimbus sample rate control ................................................................................................... ..................................... 134 ? slimbus signal path enable .................................................................................................... ......................................... 135 ? slimbus control register access ............................................................................................... ................................ 136 ? slimbus clocking control ...................................................................................................... ......................................... 138 ? output signal path ........................................................................................................ 140 ? output signal path enable ..................................................................................................... ......................................... 142 ? output signal path sample rate control ........................................................................................ ......................... 143 ? output signal path control .................................................................................................... ....................................... 144 ? output signal path digital volume control ..................................................................................... ....................... 145 ? output signal path digital volume limit ....................................................................................... ............................. 150 ? output signal path noise gate control ......................................................................................... ........................... 154 ? output signal path aec loopback ............................................................................................... ................................. 156 ? headphone/earpiece outputs and mono mode ...................................................................................... .................. 157 ? speaker outputs (analogue) .................................................................................................... ...................................... 159 ? speaker outputs (digital pdm) ................................................................................................. ...................................... 159 ? external accessory detection ............................................................................... 162 ? jack detect ................................................................................................................... ......................................................... 162 ? jack pop suppression (micdet clamp) .......................................................................................................................... 164 ? microphone detect ............................................................................................................. ................................................ 165 ? headphone detect .............................................................................................................. ................................................. 170 ? low power sleep co nfiguration ............................................................................. 173 ? sleep mode ............................................................................................................................... ............................................... 173 ? sleep control signals - jd1, gp5, micdet clamp ................................................................................ ...................... 175 ? wake-up transition ............................................................................................................ ................................................. 177 ? write sequence control ........................................................................................................ .......................................... 178 ? interrupt control ............................................................................................................. ................................................. 179 ? general purpose in put / output .............................................................................. 180 ? gpio control .................................................................................................................. ....................................................... 181 ? gpio function select .......................................................................................................... ............................................... 183 ? digital audio interface function (aifntxlrclk) ................................................................................ ...................... 186 ? button detect (gpio input) .................................................................................................... ........................................... 186 ?
production data WM5102 w pd, may 2013, rev 4.0 5 logic ?1? and logic ?0? output (gpi o output) .................................................................................. .............................. 187 ? interrupt (irq) status output ................................................................................................. ....................................... 187 ? dsp status flag (dsp irqn) output ............................................................................................. .................................. 187 ? opclk and opclk_async clock output ............................................................................................ ........................... 188 ? frequency locked loop (fll) status output ..................................................................................... ...................... 189 ? frequency locked loop (fll) clock output ...................................................................................... ....................... 189 ? pulse width modulation (pwm) signal output .................................................................................... ..................... 190 ? headphone detection status output ............................................................................................. ............................ 190 ? microphone / accessory dete ction status output ................................................................................ .............. 191 ? boot done stat us output ....................................................................................................... ......................................... 191 ? asynchronous sample rate converter (asrc) lock status output ............................................................. 191 ? asynchronous sample rate converter (asrc) configuration error status output ........................... 192 ? over-temperature status output ................................................................................................ ............................... 192 ? dynamic range control ( drc) status output ..................................................................................... ..................... 192 ? control write sequencer status detection ...................................................................................... .................... 193 ? control interface erro r status output ......................................................................................... ........................ 193 ? system clocks enable status output ............................................................................................ ............................ 193 ? clocking error status output .................................................................................................. ................................... 194 ? digital audio interface configura tion error status output ..................................................................... .... 195 ? interrupts .................................................................................................................... .... 196 ? clocking and sample rates ........................................................................................ 208 ? system clocking ............................................................................................................... ................................................... 208 ? sample rate control ........................................................................................................... .............................................. 208 ? automatic sample rate detection ............................................................................................... ................................. 209 ? sysclk and asyncclk control ................................................................................................... .................................... 210 ? miscellaneous clock controls .................................................................................................. .................................. 213 ? bclk and lrclk control ........................................................................................................ ............................................ 220 ? control interface clocking .................................................................................................... ...................................... 220 ? frequency locked loop (fll) ................................................................................................... ....................................... 220 ? free-running fll mode ......................................................................................................... ............................................. 231 ? spread spectrum fll control ................................................................................................... .................................... 232 ? gpio outputs from fll ......................................................................................................... .............................................. 233 ? example fll calculation ............................................................................................................................... .................... 233 ? example fll settings .......................................................................................................... ................................................ 234 ? control interface ......................................................................................................... 235 ? 2-wire (i2c) co ntrol mode ..................................................................................................... ............................................ 236 ? 4-wire (spi) control mode ..................................................................................................... ............................................ 240 ? control write sequencer .......................................................................................... 241 ? initiating a sequence ............................................................................................................................... ........................... 241 ? automatic sample rate detection sequences ..................................................................................... ................... 242 ? jack detect, gpio, micdet clamp, and wake-up sequences ........................................................................ ......... 243 ? drc signal detect sequences ................................................................................................... ..................................... 244 ? boot sequence ............................................................................................................................... ....................................... 245 ? sequencer outputs and readback ............................................................................................................................... 246 ? programming a sequence ........................................................................................................ ........................................ 246 ? sequencer memory definition ................................................................................................... ..................................... 247 ? charge pumps, regulators and voltage reference ...................................... 249 ? charge pumps and ldo2 regulator ............................................................................................... .............................. 249 ? micbias bias (micbias) control ................................................................................................ ........................................ 249 ? voltage reference circuit ..................................................................................................... ........................................ 250 ? ldo1 regulator and dcvdd supply ............................................................................................... ................................ 250 ? block diagram and control registers ........................................................................................... ........................... 251 ?
WM5102 production data w pd, may 2013, rev 4.0 6 jtag interface ................................................................................................................ . 256 ? thermal shutdown ........................................................................................................ 256 ? power-on reset (por) ................................................................................................... 256 ? hardware reset, software reset, wake-up, and device id ........................... 259 ? register ma p ......................................................................................................... 261 ? applications info rmation ............................................................................... 296 ? recommended external components .................................................................... 296 ? analogue input paths .......................................................................................................... .............................................. 296 ? digital microphone input paths ................................................................................................ .................................... 296 ? microphone bias circuit ....................................................................................................... ............................................ 296 ? headphone/earpiece driver output path ......................................................................................... ......................... 298 ? speaker driver output path .................................................................................................... ....................................... 299 ? power supply / reference decoupling ........................................................................................... ........................... 301 ? charge pump components ........................................................................................................ ....................................... 302 ? external accessory detection components ....................................................................................... ................... 302 ? recommended external components diagram ....................................................................................... ................ 304 ? digital audio interface clocking configurations ........................................... 305 ? pcb layout cons iderations ....................................................................................... 309 ? package dimens ions ........................................................................................... 310 ? important no tice ................................................................................................ 311 ? address: ...................................................................................................................... ....... 311 ? revision hi story .................................................................................................. 312 ?
production data WM5102 w pd, may 2013, rev 4.0 7 pin configuration ordering information order code temperature range package moisture sensitivity level peak soldering temperature WM5102ecs/r -40 ? c to +85 ? c w-csp (pb-free, tape and reel) msl1 260 ? c note: reel quantity = 5000
WM5102 production data w pd, may 2013, rev 4.0 8 pin description a description of each pin on the WM5102 is provided below. note that a table detailing the associated power domain fo r every input and output pin is provided on the following page. note that, where multiple pins share a common nam e, these pins should be tied together on the pcb. all digital output pins are cmos outputs, unless otherwise stated. pin no name type description b3, b4, b7, c3, c4, c5, c6, c7, c8, f2, f3, g3, h3, j3, l3 agnd supply analogue ground (return path for avdd) j13 aif1bclk digital input / output audio interface 1 bit clock j11 aif1rxdat digital input audio interface 1 rx digital audio data j12 aif1lrclk digital input / output audio interface 1 left / right clock j8 aif1txdat digital output audio interf ace 1 tx digital audio data k5 aif2bclk digital input / output audio interface 2 bit clock m9 aif2rxdat digital input audio interface 2 rx digital audio data l8 aif2lrclk digital input / output audio interface 2 left / right clock l6 aif2txdat digital output audio interf ace 2 tx digital audio data l5 aif3bclk digital input / output audio interface 3 bit clock k4 aif3rxdat digital input audio interface 3 rxdigital audio data m5 aif3lrclk digital input / output audio interface 3 left / right clock l4 aif3txdat digital output audio interf ace 3 tx digital audio data a3, a7, m3 avdd supply analogue supply l13 cif1addr digital input control interface 1 (i2c) address select k12 cif1sclk digital input control interface 1 clock input k11 cif1sda digital input / output control interface 1 data input and output / acknowledge output. the output function is implem ented as an open drain circuit. m13 cif2mosi digital input control interface 2 master out / slave in data k9 cif2miso digital output control interface 2 master in / slave out data l12 cif2sclk digital input control interface 2 clock input l11 cif2ss digital input control interface 2 slave select (ss) b9 cp1ca analogue output charge pump 1 fly-back capacitor pin b10 cp1cb analogue output charge pump 1 fly-back capacitor pin a10 cp1voutn analogue output charge pump 1 negative output decoupling pin a9 cp1voutp analogue output charge pump 1 positive output decoupling pin c11 cp2ca analogue output charge pump 2 fly-back capacitor pin b11 cp2cb analogue output charge pump 2 fly-back capacitor pin a11 cp2vout analogue output charge pump 2 output decoupling pin / supply for ldo2 c10 cpgnd supply charge pump 1 & 2 ground (return path for cpvdd) c9 cpvdd supply supply for charge pump 1 & 2 g13, m10 dbvdd1 supply digital buffer (i/o) supply (cor e functions and audio interface 1) m6 dbvdd2 supply digital buffer (i/o) suppl y (for audio interface 2) m4 dbvdd3 supply digital buffer (i/o) suppl y (for audio interface 3) g11, m8 dcvdd supply digital core supply e5, e6, e7, e8, e9, f5, f6, f7, f8, f9, g5, g6, g7, g8, g9, g12, h5, h6, h7, h8, h9, m7 dgnd supply digital ground (return path for dcvdd, dbvdd1, dbvdd2 and dbvdd3) a4 epoutp analogue output earpiece positive output
production data WM5102 w pd, may 2013, rev 4.0 9 pin no name type description a5 epoutn analogue output earpiece negative output k13 gpio1 digital input / output general purpose pin gpio1. the output configuration is se lectable cmos or open drain. l7 gpio2 digital input / output general purpose pin gpio2. the output configuration is se lectable cmos or open drain. k3 gpio3 digital input / output general purpose pin gpio3. the output configuration is se lectable cmos or open drain. k10 gpio4 digital input / output general purpose pin gpio4. the output configuration is se lectable cmos or open drain. g10 gpio5 digital input / output general purpose pin gpio5. the output configuration is se lectable cmos or open drain. b12 hpdetl analogue input headphone left (hpout1l) sense input a12 hpdetr analogue input headphone right (hpout1r) sense input a13 hpout1fb1/ micdet2 analogue input hpout1l and hpout1r ground feedback pin 1/ microphone & accessory sense input 2 b8 hpout1l analogue output left headphone 1 output a8 hpout1r analogue output right headphone 1 output b6 hpout2fb analogue input hpout2l and hpout2r ground loop noise rejection feedback a6 hpout2l analogue output left headphone 2 output b5 hpout2r analogue output right headphone 2 output e3 in1ln/ dmicclk1 analogue input / digital output left channel negative differential mic input / digital mic clock output 1 d3 in1lp analogue input left channel single-ended mic input / left channel line input / left channel positive differential mic input e1 in1rn/ dmicdat1 analogue input / digital input right channel negative differential mic input / digital mic data input 1 e2 in1rp analogue input right channel single-ended mic input / right channel line input / right channel positive differential mic input c1 in2ln/ dmicclk2 analogue input / digital output left channel negative differential mic input / digital mic clock output 2 c2 in2lp analogue input left channel single-ended mic input / left channel line input / left channel positive differential mic input d1 in2rn/ dmicdat2 analogue input / digital input right channel negative differential mic input / digital mic data input 2 d2 in2rp analogue input right channel single-ended mic input / right channel line input / right channel positive differential mic input a1 in3ln/ dmicclk3 analogue input / digital output left channel negative differential mic input / digital mic clock output 3 a2 in3lp analogue input left channel single-ended mic input / left channel line input / left channel positive differential mic input b1 in3rn/ dmicdat3 analogue input / digital input right channel negative differential mic input / digital mic data input 3 b2 in3rp analogue input right channel single-ended mic input / right channel line input / right channel positive differential mic input f13 irq digital output interrupt request (irq ) output (default is active low). the pin configuration is sele ctable cmos or open drain. e10 jackdet analogue input jack detect input
WM5102 production data w pd, may 2013, rev 4.0 10 pin no name type description f11 ldoena digital input enable pin for ldo1 d13 ldovdd supply supply for ldo1 e12 ldovout analogue output ldo1 output h13 mclk1 digital input master clock 1 f12 mclk2 digital input master clock 2 c12 micbias1 analogue output microphone bias 1 d12 micbias2 analogue output microphone bias 2 c13 micbias3 analogue output microphone bias 3 b13 micdet1/ hpout1fb2 analogue input microphone & accessory sense input 1/ hpout1l and hpout1r ground feedback pin 2 e11, f1 micvdd analogue output ldo2 output decoupling pin (generated internally by WM5102) e13 reset digital input digital reset input (active low) h12 slimclk digital input / output slim bus clock input / output h11 slimdat digital input / output slim bus data input / output l10 spkclk digital output digital speaker (pdm) clock output k8 spkdat digital output digital speaker (pdm) data output j1, j2 spkgndl supply left speaker driver ground (return path for spkvddl) k1, k2 spkgndr supply right speaker driver ground (return path for spkvddr) h2 spkoutln analogue output left speaker negative output h1 spkoutlp analogue output left speaker positive output l2 spkoutrn analogue output right speaker negative output l1 spkoutrp analogue output right speaker positive output g1, g2 spkvddl supply left speaker driver supply m1, m2 spkvddr supply right speaker driver supply l9 tck digital input jtag clock input m11 tdi digital input jtag data input k6 tdo digital output jtag data output k7 tms digital input jtag mode select input m12 trst digital input jtag test access port re set (active low, internal pull-down). this input should be logic 0 for normal WM5102 operation. d11 vrefc analogue output bandgap reference decoupling capacitor connection
production data WM5102 w pd, may 2013, rev 4.0 11 the following table identifies the power domain and ground refe rence associated with each of the input / output pins. pin no name power domain ground domain j13 aif1bclk dbvdd1 dgnd j11 aif1rxdat dbvdd1 dgnd j12 aif1lrclk dbvdd1 dgnd j8 aif1txdat dbvdd1 dgnd k5 aif2bclk dbvdd2 dgnd m9 aif2rxdat dbvdd2 dgnd l8 aif2lrclk dbvdd2 dgnd l6 aif2txdat dbvdd2 dgnd l5 aif3bclk dbvdd3 dgnd k4 aif3rxdat dbvdd3 dgnd m5 aif3lrclk dbvdd3 dgnd l4 aif3txdat dbvdd3 dgnd l13 cif1addr dbvdd1 dgnd k12 cif1sclk dbvdd1 dgnd k11 cif1sda dbvdd1 dgnd m13 cif2mosi dbvdd1 dgnd k9 cif2miso dbvdd1 dgnd l12 cif2sclk dbvdd1 dgnd l11 cif2ss dbvdd1 dgnd a4 epoutp cpvdd agnd a5 epoutn cpvdd agnd k13 gpio1 dbvdd1 dgnd l7 gpio2 dbvdd2 dgnd k3 gpio3 dbvdd3 dgnd k10 gpio4 dbvdd1 dgnd g10 gpio5 dbvdd1 dgnd b12 hpdetl avdd agnd a12 hpdetr avdd agnd a13 hpout1fb1/ micdet2 cpvdd (ground noise rejection) / micvdd (microphone / accessory detection) agnd b8 hpout1l cpvdd agnd a8 hpout1r cpvdd agnd b6 hpout2fb cpvdd agnd a6 hpout2l cpvdd agnd b5 hpout2r cpvdd agnd e3 in1ln/ dmicclk1 micvdd (analogue) / micvdd, micbias1, micbias2, micbias3 (digital) the dmicclk1 power domain is selectable using in1_dmic_sup agnd d3 in1lp avdd agnd e1 in1rn/ dmicdat1 micvdd (analogue) / micvdd, micbias1, micbias2, micbias3 (digital) the dmicdat1 power domain is selectable using in1_dmic_sup agnd e2 in1rp avdd agnd c1 in2ln/ dmicclk2 micvdd (analogue) / micvdd, micbias1, micbias2, micbias3 (digital) the dmicclk2 power domain is selectable using in2_dmic_sup agnd c2 in2lp avdd agnd d1 in2rn/ dmicdat2 micvdd (analogue) / micvdd, micbias1, micbias2, micbias3 (digital) the dmicdat2 power domain is selectable using in2_dmic_sup agnd d2 in2rp avdd agnd
WM5102 production data w pd, may 2013, rev 4.0 12 pin no name power domain ground domain a1 in3ln/ dmicclk3 micvdd (analogue) / micvdd, micbias1, micbias2, micbias3 (digital) the dmicclk3 power domain is selectable using in3_dmic_sup agnd a2 in3lp avdd agnd b1 in3rn/ dmicdat3 micvdd (analogue) / micvdd, micbias1, micbias2, micbias3 (digital) the dmicdat3 power domain is selectable using in3_dmic_sup agnd b2 in3rp avdd agnd f13 irq dbvdd1 dgnd e10 jackdet avdd agnd f11 ldoena dbvdd1 dgnd h13 mclk1 dbvdd1 dgnd f12 mclk2 dbvdd1 dgnd c12 micbias1 micvdd agnd d12 micbias2 micvdd agnd c13 micbias3 micvdd agnd b13 micdet1/ hpout1fb2 micvdd (microphone / accessory detection) / cpvdd (ground noise rejection) agnd e13 reset dbvdd1 dgnd h12 slimclk dbvdd1 dgnd h11 slimdat dbvdd1 dgnd l10 spkclk dbvdd1 dgnd k8 spkdat dbvdd1 dgnd h2 spkoutln spkvddl spkgndl h1 spkoutlp spkvddl spkgndl l2 spkoutrn spkvddr spkgndr l1 spkoutrp spkvddr spkgndr l9 tck dbvdd1 dgnd m11 tdi dbvdd1 dgnd k6 tdo dbvdd1 dgnd k7 tms dbvdd1 dgnd m12 trst dbvdd1 dgnd d11 vrefc avdd agnd
production data WM5102 w pd, may 2013, rev 4.0 13 absolute maximum ratings absolute maximum ratings are stress ratings only. permanent dam age to the device may be caused by continuously operating at or beyond these limits. device functional operating limits and guarant eed performance specifications are given under electrical characteristics at the te st conditions specified. esd sensitive device. this device is manufactured on a cmos process. it is therefore generically susceptible to damage from excessive static vo ltages. proper esd precautions must be taken during handling and storage of this device. wolfson tests its package types according to ipc/jedec j-st d-020 for moisture sensitivity to determine acceptable storage conditions prior to surface mount assembly. these levels are: msl1 = unlimited floor life at <30 ? c / 85% relative humidity. not normally stored in moisture barrier bag. msl2 = out of bag storage for 1 year at <30 ? c / 60% relative humidity. supplied in moisture barrier bag. msl3 = out of bag storage for 168 hours at <30 ? c / 60% relative humidity. supplied in moisture barrier bag. the moisture sensitivity level for each package type is specif ied in ordering information. condition min max supply voltages (dbvdd1, ldovdd, avdd, dcvdd, cpvdd) -0.3v +2.0v supply voltages (dbvdd2, dbvdd3, micvdd) -0.3v +4.0v supply voltages (spkvddl, spkvddr) -0.3v +6.0v voltage range digital inputs (dbvdd1 domain) agnd - 0.3v dbvdd1 + 0.3v voltage range digital inputs (dbvdd2 domain) agnd - 0.3v dbvdd2 + 0.3v voltage range digital inputs (dbvdd3 domain) agnd - 0.3v dbvdd3 + 0.3v voltage range digital inputs (dmicdatn) agnd - 3.3v micvdd + 0.3v voltage range analogue inputs (innln) agnd - 0.3v micvdd + 0.3v voltage range analogue inputs (innlp, innrn, innrp) agnd - 3.3v micvdd + 0.3v ground (dgnd, cpgnd, spkgndl, spkgndr) agnd - 0.3v agnd + 0.3v operating temperature range, t a -40oc +85oc operating junction temperature, t j -40oc +125oc storage temperature after soldering -65oc +150oc
WM5102 production data w pd, may 2013, rev 4.0 14 recommended operating conditions parameter symbol min typ max unit digital supply range (core) see notes 3, 4, 5 dcvdd ( 24.576mhz clocking) 1.14 1.2 1.9 v dcvdd (>24.576mhz clocking) 1.71 1.8 1.9 digital supply range (i/o) dbvdd1 1.7 1.9 v digital supply range (i/o) dbvdd2, dbvdd3 1.7 3.47 v ldo supply range ldovdd 1.7 1.8 1.9 v charge pump supply range cpvdd 1.7 1.8 1.9 v speaker supply range spkvddl, spkvddr 2.4 5.5 v analogue supply range avdd 1.7 1.8 1.9 v microphone bias supply see note 6 micvdd 2.375 2.5 3.6 v ground dgnd, agnd, cpgnd, spkgndl, spkgndr 0 v power supply rise time see notes 7, 8, 9 all supplies 1 s operating temperature range t a -40 85 c notes: 1. the grounds must always be within 0.3v of agnd. 2. avdd must be supplied before or simultaneously to dcvdd. dcvdd must not be powered if avdd is not present. there are no other power sequencing requirements. 3. an internal ldo (powered by ldovdd) can be used to provide the dcvdd supply. 4. ?sleep? mode is supported when dcvdd is below t he limits noted, provided avdd and dbvdd1 are present. 5. under default conditions, digital core clocking rates above 24.576mhz are inhibited. the register-controlled clocking limit should only be raised when the app licable dcvdd voltage is present. 6. an internal charge pump and ldo (powered by cpvdd) pr ovide the microphone bias supply; the micvdd pin should not be connected to an external supply. 7. dcvdd and micvdd minimum rise times do not apply when these domains are powered us ing the internal ldos. 8. the specified minimum power supply rise times assume a minimum decoupling capacitance of 100nf per pin. however, wolfson strongly advises that the re commended decoupling capacitors are present on the pcb and that appropriate layout guidelines are observed. 9. the specified minimum power supply rise times also assume a maximum pc b inductance of 10nh between decoupling capacitor and pin.
production data WM5102 w pd, may 2013, rev 4.0 15 electrical characteristics test conditions avdd = 1.8v, with the exception of the condition(s) noted above, the following electrical charac teristics are valid across the full range of recommended operating conditions. parameter symbol test conditions min typ max unit analogue input signal level (in1l, in1r, in2l, in2r, in3l, in3r) full-scale input signal level v infs single-ended pga input 0.5 -6 v rms dbv differential pga input 1 0 v rms dbv notes: 1. the full-scale input signal level changes in proportion with avdd. for differential input, it is calculated as avdd / 1.8. 2. a 1.0v rms differential signal equates to 0.5v rms /-6dbv per input. 3. a sinusoidal input signal is assumed. test conditions t a = +25 o c with the exception of the condition(s) noted above, the following electrical charac teristics are valid across the full range of recommended operating conditions. parameter symbol test conditions min typ max unit analogue input pin characteristics (in1l, in1r, in2l, in2r, in3l, in3r) input resistance r in differential input, all pga gain settings 24 k ? single-ended input, 0db pga gain 16 input capacitance c in 5 pf test conditions the following electrical characteristics are valid across the full range of recommended operating conditions. parameter symbol test conditions min typ max unit input programmable gain amplifiers (pgas) minimum programmable gain 0 db maximum programmable gain 31 db programmable gain step size guaranteed monotonic 1 db
WM5102 production data w pd, may 2013, rev 4.0 16 test conditions the following electrical characteristics are valid across the full range of recommended operating conditions. parameter symbol test conditions min typ max unit line / headphone / earpiece output driver (hpoutnl, hpoutnr) load resistance normal mode 15 ? mono mode (btl) 30 device survival with load applied indefinitely 0.1 load capacitance direct connection, normal mode 400 pf direct connection, mono mode (btl) 200 connection via 16 ? series resistor 2 nf dc offset at load single-ended mode 0.1 mv differential (btl) mode 0.2 earpiece output driv er (epoutp+epoutn) load resistance normal operation 15 ? device survival with load applied indefinitely 0.1 load capacitance direct connection (btl) 200 pf connection via 16 ? series resistor 2 nf dc offset at load 0.2 mv speaker output driver (spkoutlp+spkoutln, spkoutrp+spkoutrn) load resistance 3 ? load capacitance 200 pf dc offset at load 5 mv spkvdd leakage current 1 a
production data WM5102 w pd, may 2013, rev 4.0 17 test conditions dbvdd1 = dbvdd2 = dbvdd3 = ldovdd = cpvdd = avdd = 1.8v, dcvdd = 1.2v (powered from ldo1), micvdd = 3.0v (powered from ldo2), spkvddl = spkvddr = 4.2v, t a = +25oc, 1khz sinusoid signal, fs = 48khz, input pga gain = 0db, 24-bit audio data unless otherwise stated. parameter symbol test conditions min typ max unit analogue input paths (innl, innr) to adc (differential input mode, inn_mode = 00) signal to noise ratio (a-weighted) snr high performance mode (inn_osr = 1) 85 95 db normal mode (inn_osr = 0) 93 total harmonic distortion thd -1dbv input -88 db total harmonic distortion plus noise thd+n -1dbv input -86 -76 db channel separation (left/right) 100 db input noise floor a-weighted, pga gain = +18db 3.2 v rms common mode rejection ratio cmrr pga gain = +30db 65 db pga gain = 0db 70 psrr (dbvddn, ldovdd, cpvdd, avdd) psrr 100mv (peak-peak) 217hz 70 db 100mv(peak-peak) 10khz 65 analogue input paths (innl, innr) to adc (single-ended input mode, inn_mode = 01) pga gain = +6db unless otherwise stated. signal to noise ratio (a-weighted) snr high performance mode (inn_osr = 1) 94 db normal mode (inn_osr = 0) 90 total harmonic distortion thd -7dbv input -81 db total harmonic distortion plus noise thd+n -7dbv input -80 db channel separation (left/right) 100 db input noise floor a-weighted, pga gain = +18db 3.2 v rms psrr (dbvddn, ldovdd, cpvdd, avdd) psrr 100mv (peak-peak) 217hz 60 db 100mv(peak-peak) 10khz 55
WM5102 production data w pd, may 2013, rev 4.0 18 test conditions dbvdd1 = dbvdd2 = dbvdd3 = ldovdd = cpvdd = avdd = 1.8v, dcvdd = 1.2v (powered from ldo1), micvdd = 3.0v (powered from ldo2), spkvddl = spkvddr = 4.2v, t a = +25oc, 1khz sinusoid signal, fs = 48khz, input pga gain = 0db, 24-bit audio data unless otherwise stated. parameter symbol test conditions min typ max unit dac to headphone output (hpout1l, hpout1r; r l = 32 ? ) maximum output power p o 0.1% thd 29 mw signal to noise ratio snr a-weighted 112 db total harmonic distortion thd p o = 20mw -86 db total harmonic distortion plus noise thd+n p o = 20mw -84 db total harmonic distortion thd p o = 5mw -89 db total harmonic distortion plus noise thd+n p o = 5mw -85 db channel separation (left/right) p o = 20mw 75 db output noise floor a-weighted 2.5 v rms psrr (dbvddn, ldovdd, cpvdd, avdd) psrr 100mv (peak-peak) 217hz 57 db 100mv (peak-peak) 10khz 57 dac to headphone output (hpout1l, hpout1r; r l = 16 ? ) maximum output power p o 0.1% thd 34 mw signal to noise ratio snr a-weighted 102 112 db total harmonic distortion thd p o = 20mw -78 db total harmonic distortion plus noise thd+n p o = 20mw -76 db total harmonic distortion thd p o = 5mw -78 db total harmonic distortion plus noise thd+n p o = 5mw -77 -67 db channel separation (left/right) p o = 20mw 75 db output noise floor a-weighted 2.5 8 v rms psrr (dbvddn, ldovdd, cpvdd, avdd) psrr 100mv (peak-peak) 217hz 57 db 100mv (peak-peak) 10khz 57 dac to line output (hpout1l, hpout1r; load = 10k ? , 50pf) full-scale output signal level v out 0dbfs input 1 0 vrms dbv signal to noise ratio snr a-weighted 101 110 db total harmonic distortion thd 0dbfs input -83 db total harmonic distortion plus noise thd+n 0dbfs input -81 -71 db channel separation (left/right) 100 db output noise floor a-weighted 2.8 8 v rms psrr (dbvddn, ldovdd, cpvdd, avdd) psrr 100mv (peak-peak) 217hz 57 db 100mv (peak-peak) 10khz 57 dac to earpiece output (hpout1l, hpout1r, mono mode, r l = 32 ? btl) maximum output power p o 0.1% thd 89 mw 5% thd 104 signal to noise ratio snr a-weighted 113 db total harmonic distortion thd p o = 50mw -92 db total harmonic distortion plus noise thd+n p o = 50mw -90 db total harmonic distortion thd p o = 5mw -86 db total harmonic distortion plus noise thd+n p o = 5mw -88 db output noise floor a-weighted 2.5 v rms psrr (dbvddn, ldovdd, cpvdd, avdd) psrr 100mv (peak-peak) 217hz 57 db 100mv (peak-peak) 10khz 57
production data WM5102 w pd, may 2013, rev 4.0 19 test conditions dbvdd1 = dbvdd2 = dbvdd3 = ldovdd = cpvdd = avdd = 1.8v, dcvdd = 1.2v (powered from ldo1), micvdd = 3.0v (powered from ldo2), spkvddl = spkvddr = 4.2v, t a = +25oc, 1khz sinusoid signal, fs = 48khz, input pga gain = 0db, 24-bit audio data unless otherwise stated. parameter symbol test conditions min typ max unit dac to headphone output (hpout2l, hpout2r; r l = 32 ? ) maximum output power p o 0.1% thd 27 mw signal to noise ratio snr a-weighted 109 db total harmonic distortion thd p o = 20mw -90 db total harmonic distortion plus noise thd+n p o = 20mw -88 db total harmonic distortion thd p o = 5mw -90 db total harmonic distortion plus noise thd+n p o = 5mw -88 db channel separation (left/right) p o = 20mw 75 db output noise floor a-weighted 3 v rms psrr (dbvddn, ldovdd, cpvdd, avdd) psrr 100mv (peak-peak) 217hz 57 db 100mv (peak-peak) 10khz 57 dac to headphone output (hpout2l, hpout2r; r l = 16 ? ) maximum output power p o 0.1% thd 32 mw signal to noise ratio snr a-weighted 101 111 db total harmonic distortion thd p o = 20mw -88 db total harmonic distortion plus noise thd+n p o = 20mw -87 db total harmonic distortion thd p o = 5mw -85 db total harmonic distortion plus noise thd+n p o = 5mw -83 -73 db channel separation (left/right) p o = 20mw 75 db output noise floor a-weighted 2.8 10 v rms psrr (dbvddn, ldovdd, cpvdd, avdd) psrr 100mv (peak-peak) 217hz 57 db 100mv (peak-peak) 10khz 57 dac to line output (hpout2l, hpout2r; load = 10k ? , 50pf) full-scale output signal level v out 0dbfs input 1 0 vrms dbv signal to noise ratio snr a-weighted 100 110 db total harmonic distortion thd 0dbfs input -87 db total harmonic distortion plus noise thd+n 0dbfs input -85 -75 db channel separation (left/right) 105 db output noise floor a-weighted 3.5 10 v rms psrr (dbvddn, ldovdd, cpvdd, avdd) psrr 100mv (peak-peak) 217hz 57 db 100mv (peak-peak) 10khz 57 dac to earpiece output (hpout2l, hpout2r, mono mode, r l = 32 ? btl) maximum output power p o 0.1% thd 85 mw 5% thd 100 signal to noise ratio snr a-weighted 112 db total harmonic distortion thd p o = 50mw -90 db total harmonic distortion plus noise thd+n p o = 50mw -88 db total harmonic distortion thd p o = 5mw -90 db total harmonic distortion plus noise thd+n p o = 5mw -88 db output noise floor a-weighted 6 v rms psrr (dbvddn, ldovdd, cpvdd, avdd) psrr 100mv (peak-peak) 217hz 57 db 100mv (peak-peak) 10khz 57
WM5102 production data w pd, may 2013, rev 4.0 20 test conditions dbvdd1 = dbvdd2 = dbvdd3 = ldovdd = cpvdd = avdd = 1.8v, dcvdd = 1.2v (powered from ldo1), micvdd = 3.0v (powered from ldo2), spkvddl = spkvddr = 4.2v, t a = +25oc, 1khz sinusoid signal, fs = 48khz, input pga gain = 0db, 24-bit audio data unless otherwise stated. parameter symbol test conditions min typ max unit dac to earpiece output (epoutp+epoutn, r l = 32 ? btl) maximum output power p o 0.1% thd 80 mw 5% thd 100 signal to noise ratio snr a-weighted 99 109 db total harmonic distortion thd p o = 50mw -86 db total harmonic distortion plus noise thd+n p o = 50mw -84 db total harmonic distortion thd p o = 5mw -85 db total harmonic distortion plus noise thd+n p o = 5mw -83 -73 db output noise floor a-weighted 3.5 10.5 v rms psrr (dbvddn, ldovdd, cpvdd, avdd) psrr 100mv (peak-peak) 217hz 52 db 100mv (peak-peak) 10khz 52 dac to earpiece output (epoutp+epoutn, r l = 16 ? btl) maximum output power p o 0.1% thd 80 mw 10% thd 105 signal to noise ratio snr a-weighted 111 db total harmonic distortion thd p o = 50mw -92 db total harmonic distortion plus noise thd+n p o = 50mw -90 db total harmonic distortion thd p o = 5mw -84 db total harmonic distortion plus noise thd+n p o = 5mw -82 db output noise floor a-weighted 3 v rms psrr (dbvddn, ldovdd, cpvdd, avdd) psrr 100mv (peak-peak) 217hz 52 db 100mv (peak-peak) 10khz 52
production data WM5102 w pd, may 2013, rev 4.0 21 test conditions dbvdd1 = dbvdd2 = dbvdd3 = ldovdd = cpvdd = avdd = 1.8v, dcvdd = 1.2v (powered from ldo1), micvdd = 3.0v (powered from ldo2), spkvddl = spkvddr = 4.2v, t a = +25oc, 1khz sinusoid signal, fs = 48khz, input pga gain = 0db, 24-bit audio data unless otherwise stated. parameter symbol test conditions min typ max unit dac to speaker output (spkoutlp+spkoutln, spkoutrp+spkoutrn, load = 8 ? , 22h, btl) high performance mode (out4_osr=1) maximum output power p o spkvdd = 5.0v, 1% thd 1.4 w spkvdd = 4.2v, 1% thd 1.0 spkvdd = 3.6v, 1% thd 0.7 signal to noise ratio snr a-weighted 82 97 db total harmonic distortion thd p o = 0.9w -70 db total harmonic distortion plus noise thd+n p o = 0.9w -68 db total harmonic distortion thd p o = 0.5w -70 db total harmonic distortion plus noise thd+n p o = 0.5w -68 -57 db channel separation (left/right) p o = 0.5w 105 db output noise floor a-weighted 55 300 v rms psrr (dbvddn, ldovdd, cpvdd, avdd) psrr 100mv (peak-peak) 217hz 60 db 100mv (peak-peak) 10khz 60 psrr (spkvddl, spkvddr) psrr 100mv (peak-peak) 217hz 70 db 100mv (peak-peak) 10khz 70 dac to speaker output (spkoutlp+spkoutln, spkoutrp+spkoutrn, load = 4 ? , 15h, btl) high performance mode (out4_osr=1) maximum output power p o spkvdd = 5.0v, 1% thd 2.5 w spkvdd = 4.2v, 1% thd 1.8 spkvdd = 3.6v, 1% thd 1.3 signal to noise ratio snr a-weighted 95 db total harmonic distortion thd p o = 1.0w -64 db total harmonic distortion plus noise thd+n p o = 1.0w -62 db total harmonic distortion thd p o = 0.5w -66 db total harmonic distortion plus noise thd+n p o = 0.5w -64 db channel separation (left/right) p o = 0.5w 105 db output noise floor a-weighted 55 v rms psrr (dbvddn, ldovdd, cpvdd, avdd) psrr 100mv (peak-peak) 217hz 60 db 100mv (peak-peak) 10khz 60 psrr (spkvddl, spkvddr) psrr 100mv (peak-peak) 217hz 70 db 100mv (peak-peak) 10khz 70
WM5102 production data w pd, may 2013, rev 4.0 22 test conditions the following electrical characteristics are valid across the full range of recommended operating conditions. parameter symbol test conditions min typ max unit digital input / output (except dmicdatn and dmicclkn) digital i/o is referenced to dbvdd1, dbvdd2 or dbvdd3. see ?pin description? for the domain applicable to each pin. see ?recommended operating conditions? for the valid operating voltage range of each dbvddn domain. input high level v ih v dbvddn =1.8v 10% 0.65 ? v dbvddn v v dbvddn =3.3v 10% 0.7 ? v dbvddn input low level v il v dbvddn =1.8v 10% 0.35 ? v dbvddn v v dbvddn =3.3v 10% 0.3 ? v dbvddn note that digital input pins shoul d not be left unconnected or floating. output high level v oh i oh = 1ma 0.9 ? v dbvddn v output low level v ol i ol = -1ma 0.1 ? v dbvddn v input capacitance 10 pf input leakage -1 1 a pull-up / pull-down resistance (where applicable) 28 36 45 k ? digital microphone input / output (dmicdatn and dmicclkn) dmicdatn and dmicclkn are each referenced to a selectable supply, v sup , according to the inn_dmic_sup registers dmicdatn input high level v ih 0.65 ? v sup v dmicdatn input low level v il 0.35 ? v sup v dmicclkn output high level v oh i oh = 1ma 0.8 ? v sup v dmicclkn output low level v ol i ol = -1ma 0.2 ? v sup v input capacitance 10 pf input leakage -1 1 a slimbus digital input / output (slimclk and slimdat) 1.8v i/o signalling (ie. 1.65v dbvdd1 1.95v) input high level v ih 0.65 ? v dbvdd1 v input low level v il 0.35 ? v dbvdd1 v output high level v oh i oh = 1ma 0.9 ? v dbvdd1 v output low level v ol i ol = -1ma 0.1 ? v dbvdd1 v pin capacitance 5 pf general purpose input / output (gpion) clock output frequency gpio pin configured as opclk or fll output 26.5 mhz
production data WM5102 w pd, may 2013, rev 4.0 23 test conditions fs 48khz with the exception of the condition(s) noted above, the following electrical charac teristics are valid across the full range of recommended operating conditions. parameter symbol test conditions min typ max unit adc decimation filters passband +/- 0.05db 0 0.454 fs -6db 0.5 fs passband ripple +/- 0.05 db stopband 0.546 fs stopband attenuation f > 0.546 fs 85 db signal path delay analogue input to digital aif output 2 ms dac interpolation filters passband +/- 0.05db 0 0.454 fs -6db 0.5 fs passband ripple +/- 0.05 db stopband 0.546 fs stopband attenuation f > 0.546 fs 85 db signal path delay digital aif input to analogue output 1.5 ms
WM5102 production data w pd, may 2013, rev 4.0 24 test conditions dbvdd1 = dbvdd2 = dbvdd3 = ldovdd = cpvdd = avdd = 1.8v, dcvdd = 1.2v (powered from ldo1), micvdd = 3.0v (powered from ldo2), spkvddl = spkvddr = 4.2v, t a = +25oc, 1khz sinusoid signal, fs = 48khz, input pga gain = 0db, 24-bit audio data unless otherwise stated. parameter symbol test conditions min typ max unit microphone bias (micbias1, micbias2, micbias3) note - no capacitor on micbiasn note - in regulator mode, it is required that v micvdd - v micbiasn > 200mv minimum bias voltage v micbias regulator mode (micbn_bypass=0) load current 1.0ma 1.5 v maximum bias voltage 2.8 v bias voltage output step size 0.1 v bias voltage accuracy -5% +5% v bias current regulator mode (micbn_bypass=0), v micvdd - v micbias >200mv 2.4 ma bypass mode (micbn_bypass=1) 5.0 output noise density regulator mode (micbn_bypass=0), micbn_lvl = 4h, load current = 1ma, measured at 1khz 50 nv/ ? hz integrated noise voltage regulator mode (micbn_bypass=0), micbn_lvl = 4h, load current = 1ma, 100hz to 7khz, a-weighted 4 vrms power supply rejection ratio (dbvddn, ldovdd, cpvdd, avdd) psrr 100mv (peak-peak) 217hz 95 db 100mv (peak-peak) 10khz 65 load capacitance regulator mode (micbn_bypass=0), micbn_ext_cap=0 50 pf regulator mode (micbn_bypass=0), micbn_ext_cap=1 1.8 4.7 f output discharge resistance micbn_ena=0, micbn_disch=1 5 k ? external accessory detect load impedance detection range (hpdetl or hpdetr) hp_impedance_ range=00 4 30 ? hp_impedance_ range=01 8 100 hp_impedance_ range=10 100 1000 hp_impedance_ range=11 1000 10000 load impedance detection accuracy (hpdetl or hpdetr) -30 +30 % load impedance detection range (micdet1 or micdet2) 2.2k ? (2%) micbias resistor. note these characteristics assume no other component is connected to micdetn. see ?applications information? for recommended external components when a typical microphone is present. for micd_lvl[0] = 1 0 3 ? for micd_lvl[1] = 1 17 21 for micd_lvl[2] = 1 36 44 for micd_lvl[3] = 1 62 88 for micd_lvl[4] = 1 115 160 for micd_lvl[5] = 1 207 381 for micd_lvl[8] = 1 475 30000 jack detection input threshold v jackdet jack insertion 0.5 x avdd v
production data WM5102 w pd, may 2013, rev 4.0 25 test conditions dbvdd1 = dbvdd2 = dbvdd3 = ldovdd = cpvdd = avdd = 1.8v, dcvdd = 1.2v (powered from ldo1), micvdd = 3.0v (powered from ldo2), spkvddl = spkvddr = 4.2v, t a = +25oc, 1khz sinusoid signal, fs = 48khz, input pga gain = 0db, 24-bit audio data unless otherwise stated. parameter symbol test conditions min typ max unit voltage (jackdet) jack removal 0.85 x avdd micvdd charge pump and regulator (cp2 and ldo2) output voltage v micvdd 1.7 2.7 3.3 v programmable output voltage step size 50 mv maximum output current 8 ma start-up time 4.7f on micvdd, i micbiasn = 1ma 4.5 ms frequency locked loop (fll1, fll2) output frequency normal operation, input reference supplied 13 52 mhz free-running mode, no reference supplied lock time f ref = 32khz, f out = 24.576mhz 10 ms f ref = 12mhz, f out = 24.576mhz 1 reset pin input reset input pulse width (to trigger a hardware reset, the reset input must be asserted for longer than this duration) 1 s test conditions the following electrical characteristics are valid across the full range of recommended operating conditions. device reset thresholds avdd reset threshold v avdd 0.50 1.51 v dcvdd reset threshold v dcvdd 0.59 0.81 v dbvdd1 reset threshold v dbvdd1 0.50 1.51 v note that the reset thresholds are derived from simu lations only, across all operat ional and process corners. device performance is not assured outside the voltage ranges def ined in the ?recommended operati ng conditions? section. refer to this section for the WM5102 power-up sequencing requirements.
WM5102 production data w pd, may 2013, rev 4.0 26 terminology 1. signal-to-noise ratio (db) ? snr is a measure of the difference in level between the maximum full scale output signal and th e output with no input signal applied. (note that th is is measured without any mute function enabled.) 2. total harmonic distortion (db) ? thd is the ratio of the rms sum of the harmonic distor tion products in the specified bandwidth (see note below) relative to the rms amp litude of the fundamental (ie. test frequency) output. 3. total harmonic distortion plus noise (db) ? thd+n is the ratio of the rms sum of the harmonic distortion products plus noise in the specified bandwidth (see note below) relative to the rms amplitude of the fundamental (ie. test frequency) output. 4. power supply rejection ratio (db) - psrr is the ratio of a specified power supply variation relative to the output signal th at results from it. psrr is measured under quiescent signal path conditions. 5. common mode rejection ratio (db) ? cmrr is the ratio of a specified input signal (applied to both sides of a differential input), relative to the output signal that results from it. 6. channel separation (l/r) (db) ? left-to-right and right-to-le ft channel separation is the difference in level between the ac tive channel (driven to maximum full scale output) and the measured si gnal level in the idle channel at the test signal frequency. the active channel is configur ed and supplied with an appropriate input signal to drive a full scale output, with signal measur ed at the output of the associated idle channel. 7. multi-path crosstalk (db) ? is the difference in level between the output of the active path and the measured signal level i n the idle path at the test signal frequency. the active path is c onfigured and supplied with an appropriate input signal to drive a full scale output, with signal measured at the output of the specified idle path. 8. mute attenuation ? this is a measure of the difference in level between the full scale output signal and the output with mut e applied. 9. all performance measurements are specif ied with a 20khz low pass ?brick-wall? filt er and, where noted, an a-weighted filter. failure to use these filters will result in higher thd and lowe r snr readings than are found in t he electrical characteristics. the low pass filter removes out of band noise.
production data WM5102 w pd, may 2013, rev 4.0 27 typical performance typical power consumption typical power consumption data is provided below for a number of different operating conditions. test conditions: dbvdd1 = dbvdd2 = dbvdd3 = ldovdd = cpvdd = avdd = 1.8v, spkvddl = spkvddr = 4.2v, dcvdd = 1.2v (powered from ldo1), micvdd = 3.0v (powered from ldo2), t a = +25oc operating mode test conditions supply current (1.8v) supply current (4.2v) total power music playback to headphone aif1 to dac to hpout1 (stereo) fs=48khz, 24-bit i2s, slave mode load = 32 ? quiescent 4.8ma 0.0ma 8.6mw 1khz sine wave, p o =10mw 37.7ma 0.0ma 67.9mw music playback to line output aif1 to dac to hpout2 (stereo) fs=48khz, 24-bit i2s, slave mode load = 10k ? , 50pf quiescent 4.4ma 0.0ma 7.9mw music playback to earpiece aif1 to dac to epout (mono) fs=48khz, 24-bit i2s, slave mode load = 32 ? , 22h, btl quiescent 5.3ma 0.0ma 9.5mw 1khz sine wave, p o =30mw 59.7ma 0.0ma 107.5mw music playback to speaker aif1 to dac to spkout (stereo) fs=48khz, 24-bit i2s, slave mode load = 8 ? , 22h, btl quiescent 5.5ma 5.8ma 34.3mw 1khz sine wave, p o =700mw 5.6ma 380ma 1606mw full duplex voice call analogue mic to adc to aif1 (out) aif (in) to dac to epout (mono) fs=8khz, 16-bit i2s, slave mode low power mode (inn_osr=00) load = 32 ? , 22h, btl quiescent 6.7ma 0.0ma 12mw stereo line record analogue line to adc to aif1 fs=48khz, 24-bit i2s, slave mode low power mode (inn_osr=00) 1khz sine wave, -1dbfs out 4.2ma 0.0ma 7.6mw sleep mode accessory detect enabled (jd1_ena=1) 0.015ma 0.0ma 0.03mw
WM5102 production data w pd, may 2013, rev 4.0 28 typical signal latency operating mode test conditions latency input output digital core aif to dac stereo path digital input (aifn) to analogue output (epout). signal is routed via the digital core asrc function in the asynchronous test cases only. fs = 48khz fs = 48khz synchronous 352s fs = 44.1khz fs = 44. 1khz synchronous 362s fs = 16khz fs = 16khz synchronous 711s fs = 8khz fs = 8khz synchronous 3580s fs = 8khz fs = 44.1khz asynchronous 3750s fs = 16khz fs = 44.1khz asynchronous 848s adc to aif stereo path analogue input (inn) to digital output (aifn). digital core high pass filter included in signal path. signal is routed via the digital core asrc function in the asynchronous test cases only. fs = 48khz fs = 48khz synchronous 268s fs = 44.1khz fs = 44. 1khz synchronous 292s fs = 16khz fs = 16khz synchronous 894s fs = 8khz fs = 8khz synchronous 1730s fs = 44.1khz fs = 8khz asynchronous 880s fs = 44.1khz fs = 16khz asynchronous 530s
production data WM5102 w pd, may 2013, rev 4.0 29 signal timing requirements system clock & frequency locked loop (fll) figure 1 master clock timing test conditions the following timing information is valid acro ss the full range of recommended operating conditions. parameter test conditions min typ max unit master clock timing (mclk1, mclk2) mclk cycle time mclk as input to fll, flln_refclk_div=00 74 ns mclk as input to fll, flln_refclk_div=01 37 mclk as input to fll, flln_refclk_div=10 or 11 25 mclk as direct sysclk or asyncclk source 40 mclk duty cycle mclk as input to fll 80:20 20:80 % mclk as direct sysclk or asyncclk source 60:40 40:60 frequency locked loops (fll1, fll2) fll input frequency flln_refclk_div=00 0.032 13.5 mhz flln_refclk_div=01 0.064 27 flln_refclk_div=10 0.128 40 flln_refclk_div=11 0.256 40 fll synchroniser input frequency flln_syncclk_div=00 0.032 13.5 mhz flln_syncclk_div=01 0.064 27 flln_syncclk_div=10 0.128 40 flln_syncclk_div=11 0.256 40
WM5102 production data w pd, may 2013, rev 4.0 30 test conditions the following timing information is valid acro ss the full range of recommended operating conditions. parameter test conditions min typ max unit internal clocking sysclk frequency sysclk_freq=000, sysclk_frac=0 -1% 6.144 +1% mhz sysclk_freq=000, sysclk_frac=1 -1% 5.6448 +1% sysclk_freq=001, sysclk_frac=0 -1% 12.288 +1% sysclk_freq=001, sysclk_frac=1 -1% 11.2896 +1% sysclk_freq=010, sysclk_frac=0 -1% 24.576 +1% sysclk_freq=010, sysclk_frac=1 -1% 22.5792 +1% sysclk_freq=011, sysclk_frac=0 -1% 49.152 +1% sysclk_freq=011, sysclk_frac=1 -1% 45.1584 +1% asyncclk frequency async_clk_freq=000 -1% 6.144 +1% mhz -1% 5.6448 +1% async_clk_freq=001 -1% 12.288 +1% -1% 11.2896 +1% async_clk_freq=010 -1% 24.576 +1% -1% 22.5792 +1% async_clk_freq=011 -1% 49.152 +1% -1% 45.1584 +1% note: when mclk1 or mclk2 is selected as a source for sysclk or asyncclk (either directly or via one of the flls), the frequency must be within 1% of the applicable sysclk _freq or asyncclk_freq register setting.
production data WM5102 w pd, may 2013, rev 4.0 31 audio interface timing digital microphone (dmic) interface timing figure 2 digital microphone interface timing test conditions the following timing information is valid acro ss the full range of recommended operating conditions. parameter symbol min typ max unit digital microphone interface timing dmicclkn cycle time t cy 320 326 716 ns dmicclkn duty cycle 45 55 % dmicclkn rise/fall time (25pf load, 1.8v supply - see note) t r , t f 5 30 ns dmicdatn (left) setup time to falling dmicclk edge t lsu 15 ns dmicdatn (left) hold time from falling dmicclk edge t lh 0 ns dmicdatn (right) setup time to rising dmicclk edge t rsu 15 ns dmicdatn (right) hold time from rising dmicclk edge t rh 0 ns notes: dmicdatn and dmicclkn are each referenced to a selectable supply, v sup . the applicable supply is selected us ing the inn_dmic_sup registers.
WM5102 production data w pd, may 2013, rev 4.0 32 digital speaker (pdm) interface timing figure 3 digital speaker (pdm) interface timing - mode a test conditions the following timing information is valid acro ss the full range of recommended operating conditions. parameter symbol min typ max unit pdm audio interface timing spkclkn cycle time t cy 160 163 358 ns spkclkn duty cycle 45 55 % spkclkn rise/fall time (dbvdd=1.8v, 25pf load) t r , t f 5 30 ns spkdatn set-up time to spkclkn rising edge (left channel) t lsu 30 ns spkdatn hold time from spkclkn rising edge (left channel) t lh 30 ns spkdatn set-up time to spkclkn falling edge (right channel) t rsu 30 ns spkdatn hold time from spkclkn falling edge (right channel) t rh 30 ns figure 4 digital speaker (pdm) interface timing - mode b test conditions the following timing information is valid acro ss the full range of recommended operating conditions. parameter symbol min typ max unit pdm audio interface timing spkclkn cycle time t cy 160 163 358 ns spkclkn duty cycle 45 55 % spkclkn rise/fall time (dbvdd=1.8v, 25pf load) t r , t f 5 30 ns spkdatn enable from spkclk rising edge (right channel) t ren 15 ns spkdatn disable to spkclk falling edge (right channel) t rdis 5 ns spkdatn enable from spkclk falling edge (left channel) t len 15 ns spkdatn disable to spkclk rising edge (left channel) t ldis 5 ns
production data WM5102 w pd, may 2013, rev 4.0 33 digital audio interface - master mode figure 5 audio interface timing - master mode note that bclk and lrclk outputs can be inverted if required; figure 5 shows the default, non- inverted polarity of these signals. test conditions the following timing information is valid acro ss the full range of recommended operating conditions. parameter symbol min typ max unit audio interface timing - master mode aifnbclk cycle time t bcy 80 ns aifn[tx/rx]lrclk propagation delay from bclk falling edge t lrd 0 12 ns aifntxdat propagation delay from bclk falling edge t dd 0 12 ns aifnrxdat setup time to bclk rising edge t dsu 7 ns aifnrxdat hold time from bclk rising edge t dh 5 ns note: the descriptions above assume non-inverted pol arity of aifnbclk and aifn[tx/rx]lrclk.
WM5102 production data w pd, may 2013, rev 4.0 34 digital audio interface - slave mode bclk (input) lrclk (input) txdat (output) rxdat (input) t dsu t dd t dh t lrh t lrsu t bch t bcl t bcy v ih v il v ih v il v oh v ol v ih v il figure 6 audio interface timing - slave mode note that bclk and lrclk inputs can be inverted if required; figure 6 shows the default, non- inverted polarity. test conditions the following timing information is valid acro ss the full range of recommended operating conditions. parameter symbol min typ max unit audio interface timing - slave mode aifnbclk cycle time t bcy 80 ns aifnbclk pulse width high t bch 12 ns aifnbclk pulse width low t bcl 12 ns aifn[tx/rx]lrclk set-up time to bclk rising edge t lrsu 7 ns aifn[tx/rx]lrclk hold time from bclk rising edge t lrh 5 ns aifnrxdat hold time from bclk rising edge t dh 5 ns aifntxdat propagation delay from bclk falling edge t dd 0 12 ns aifnrxdat set-up time to bclk rising edge t dsu 7 ns notes: the descriptions above assume non-inverted pol arity of aifnbclk and aifn[tx/rx]lrclk. when aifnbclk is selected as a source for sysclk or asyncclk (either directly or via one of the flls), the frequency must be within 1% of the applicable sysclk_fre q or asyncclk_freq register setting.
production data WM5102 w pd, may 2013, rev 4.0 35 digital audio interface - tdm mode when tdm operation is used on the ai fntxdat pins, it is important that two devices do not attempt to drive the aifntxdat pin simultaneously. to suppor t this requirement, the aifntxdat pins can be configured to be tri-stated when not outputting data. the timing of the aifntxdat tri-stating at the start and end of the data transmission is described in figure 7 below. figure 7 audio interface timing - tdm mode test conditions the following timing information is valid acro ss the full range of recommended operating conditions. parameter min typ max unit tdm timing - master mode aifntxdat setup time from bclk falling edge 0 ns aifntxdat release time from bclk falling edge 15 ns tdm timing - slave mode aifntxdat setup time from bclk falling edge 5 ns aifntxdat release time from bclk falling edge 32 ns
WM5102 production data w pd, may 2013, rev 4.0 36 control interface timing 2-wire (i2c) control mode figure 8 control interface timing - 2-wire (i2c) control mode test conditions the following timing information is valid acro ss the full range of recommended operating conditions. parameter symbol min typ max unit sclk frequency 1000 khz sclk low pulse-width t 1 500 ns sclk high pulse-width t 2 260 ns hold time (start condition) t 3 260 ns setup time (start condition) t 4 260 ns sda, sclk rise time t 6 120 ns sda, sclk fall time t 7 120 ns setup time (stop condition) t 8 260 ns sda setup time (data input) t 5 50 ns sda hold time (input/output) t 9 0 ns sda valid time (data/ack output) t 10 450 ns pulse width of spikes that will be suppressed t ps 0 50 ns
production data WM5102 w pd, may 2013, rev 4.0 37 4-wire (spi) control mode figure 9 control interface timing - 4-wire (spi) control mode (write cycle) figure 10 control interface timing - 4-wire (spi) control mode (read cycle) test conditions the following timing information is valid acro ss the full range of recommended operating conditions. parameter symbol min typ max unit ss falling edge to sclk rising edge t ssu 2.6 ns sclk falling edge to ss rising edge t sho 0 ns sclk pulse cycle time t scy 38.4 ns sclk pulse width low t scl 15.3 ns sclk pulse width high t sch 15.3 ns mosi to sclk set-up time t dsu 1.3 ns mosi to sclk hold time t dho 1.7 ns sclk falling edge to miso transition t dl 0 7.8 ns
WM5102 production data w pd, may 2013, rev 4.0 38 slimbus interface timing for details of the slimbus interface timing requirements, refer to the mipi alliance specification for serial low-power inter-c hip media bus (slimbus).
production data WM5102 w pd, may 2013, rev 4.0 39 device description introduction the WM5102 is a highly integrated low-power audi o hub codec for mobile telephony and portable devices. it provides flexible, high-performance audio interfacing for handheld devices in a small and cost-effective package. it provides wideband voice pr ocessing for mobile telephony, ideally suited for multimedia phones and smartphones. the WM5102 digital core provides an extensive c apability for signal processing algorithms, including echo cancellation, wind noise, side-tone and other progr ammable filters. parametric equalisation (eq) and dynamic range control (drc) are also supported. highly flexible digital mixing, including stereo full-duplex asynchronous sample rate conversion, provides use-case flexibility across a broad range of system architectures. a signal generator fo r controlling haptics vibe actuators is included. the WM5102 provides multiple digital audio interf aces, including slimbus, in order to provide independent and fully asynchronous connec tions to different processors (eg. application processor, baseband processor and wireless transceiver). a flexible clocking arrangement supports a wide va riety of external clock references, including clocking derived from the digital audio interface. two integrated frequency locked loop (fll) circuits provide additional flexibility. unused circuitry can be di sabled under software control, in order to save power; low leakage currents enable extended standby/off time in portable battery -powered applications. configurable ?wake-up? actions can be associated with the low-power standby (sleep) mode. versatile gpio functionality is provided, and support for external accessory / push-button detection inputs. comprehensive interrupt (irq) logi c and status readback are also provided. hi-fi audio codec the WM5102 is a high-performance low-power audio codec which uses a simple analogue architecture. 6 adcs and 7 dacs are incorporat ed, providing a dedicated adc for each input and a dedicated dac for each output channel. the analogue outputs comprise two 29mw (113db snr) stereo headphone amplifiers with ground- referenced output, a 100mw differential (btl) earpiec e driver, and a class d stereo speaker driver capable of delivering 2w per channel into a 4 ? load. six analogue inputs are provided, each supporting single-ended or differential input modes. in differential mode, the input path snr is 96db. the adc input paths can be bypassed, supporti ng up to 6 channels of digital microphone input. the audio codec is controlled directly via regi ster access. the simple analogue architecture, combined with the integrated tone generator, enables simple device configuration and testing, minimising debug time and reducing software effort. the WM5102 output drivers are designed to support as many different system architectures as possible. each output has a dedicated dac which allo ws mixing, equalisation, filtering, gain and other audio processing to be configured independently for eac h channel. this allows each signal path to be individually tailored for the load characteristics. all outputs have integrated pop and click suppression features. the headphone output drivers are ground-referenced, powered from an integrated charge pump, enabling high quality, power efficient headphone playba ck without any requirement for dc blocking capacitors. ground loop feedback is incorporated, providing rejection of noise on the ground connections. a mono mode is ava ilable on the headphone outputs; this configures the drivers as differential (btl) outputs, suitable for an earpiece or hearing aid coil. the class d speaker drivers de liver excellent power efficienc y. high psrr, low leakage and optimised supply voltage ranges enable powering from switching regulators or directly from the battery. battery current consumpt ion is minimised across a wide va riety of voice communication and multimedia playback use cases.
WM5102 production data w pd, may 2013, rev 4.0 40 the WM5102 is cost-optimised for a wide range of mobile phone applications, and features two channels of class d power amplification. for applic ations requiring more than two channels of power amplification (or when using the integrated class d path to drive a haptics actuator), the pdm output channels can be used to drive two ex ternal pdm-input speaker driver s. in applications where stereo loudspeakers are physically widely separated, the pdm outputs can ease layout and emc by avoiding the need to run the class-d speaker output s over long distanc es and interconnects. digital audio core the WM5102 uses a core architecture based on all-di gital signal routing, making digital audio effects available on all signal paths, regardless of whether the source data input is analogue or digital. the digital mixing desk allows different audio effe cts to be applied simultaneously on many independent paths, whilst also supporting a variety of sample rates concurrently. this helps support many new audio use-cases. soft mute and un-mute control allo ws smooth transitions between use-cases without interrupting existing audio streams elsewhere. the WM5102 digital core provides an extensiv e capability for programmable signal processing algorithms. the dsp can support functions such as echo cancellation, wind noise, side-tone and other programmable filters. the dsp is optimised for advanced voice processing, but a wide range of application-specific filters and audio enhancements can also be implemented. highly flexible digital mixing, including mixing between audio inte rfaces, is possible. the WM5102 performs stereo full-duplex asynchronous sample rate conversion, providing use-case flexibility across a broad range of system architectures. automati c sample rate detection is provided, enabling seamless wideband/narrowband voice call handover. dynamic range controller (drc) functions are av ailable for optimising audio signal levels. in playback modes, the drc can be used to maximise l oudness, while limiting the signal level to avoid distortion, clipping or battery droop, in particula r for high-power output drivers such as speaker amplifiers. in record modes, the drc assists in app lications where the signal level is unpredictable. the 5-band parametric equaliser (eq) functions can be used to compensate for the frequency characteristics of the output transducers. eq functions can be cascaded to provide additional frequency control. programmable high-pass and low-pass f ilters are also available for general filtering applications such as removal of wind and other low-frequency noise. digital interfaces three serial digital audio interfaces (aifs) each support pcm, tdm and i2s data formats for compatibility with most industry-standard chipsets. aif1 supports eight input/output channels; aif2 and aif3 each support two input/output channels. bi directional operation at sample rates up to 192khz is supported. six digital pdm input channels are available (three stereo interfaces ); these are typically used for digital microphones, powered from the integrated mi cbias power supply regulators. two pdm output channels are also available (one stereo interface) ; these are typically used for external power amplifiers. embedded mute codes provide a contro l mechanism for external pdm-input devices. the WM5102 features a mipi-compliant slimbus interface, providing eight channels of audio input/output. mixed audio sample rates are suppor ted on the slimbus interface. the slimbus interface also supports read/write a ccess to the WM5102 control registers. the WM5102 is equipped with an i2c slave port (at up to 1mhz), and an spi port (at up to 26mhz). full access to the register map is also provided via the slimbus port.
production data WM5102 w pd, may 2013, rev 4.0 41 other features the WM5102 incorporates two 1khz tone generators which can be used for ? beep? functions through any of the audio signal paths. the phase relations hip between the two generators is configurable, providing flexibility in creating differ ential signals, or for test scenarios. a white noise generator is provided, which can be r outed within the digital core. the noise generator can provide ?comfort noise? in cases where silence (digital mute) is not desirable. two pulse width modulation (pwm) signal generators are incorporated. the duty cycle of each pwm signal can be modulated by an audio s ource, or can be set to a fixed value using a control register setting. the pwm signal generators can be output directly on a gpio pin. the WM5102 provides 5 gpio pins , supporting selectable input/output functions for interfacing, detection of external hardware, and to provide logi c outputs to other devices. comprehensive interrupt (irq) functionality is also provided for moni toring internal and exte rnal event conditions. a signal generator for controlling hapt ics devices is included, compatible with both eccentric rotating mass (erm) and linear resonant actuator (lra) haptic devices. the haptics signal generator is highly configurable, and can exec ute programmable drive event pr ofiles, including reverse drive control. an external vibe actuator can be dr iven directly by the class d speaker output. the WM5102 can be powered from a 1.8v external s upply. a separate supply (4.2v) is typically required for the class d speaker driver. integr ated charge pump and ldo regulators circuits are used to generate supply rails for in ternal functions and to support pow ering or biasing of external microphones. a smart accessory interface is included, s upporting most standard 3.5mm accessories. jack detection, accessory sensing and impedance measurem ent is provided, for external accessory and push-button detection. accessory detection can be used as a ?wake-up? trigger from low-power standby. microphone activity detection with interrupt is also available. system clocking can be derived from the mclk1 or mclk2 input pins. alternatively, the slimbus interface, or the audio interfaces (configured in slave mode), can be used to provide a clock reference. two integrated frequency locked loop (fll) circuits provide s upport for a wide range of clocking configurations, including the us e of a 32khz input clock reference.
WM5102 production data w pd, may 2013, rev 4.0 42 input signal path the WM5102 has six highly flexible input channels, configurable in a large number of combinations. each of the six input channels supports analogue (mic or line) and digital input configurations. the analogue input paths support single-ended and differential modes , programmable gain control and are digitised using a high perfo rmance 24-bit sigma-delta adc. the digital input paths interface directly wi th external digital microphones; a separate microphone interface clock is provided for 3 separate stereo pairs of digital microphones . digital delay can be applied to any of the digital input paths; this c an be used for phase adjustment of any digital input, including directional control of multiple microphones. three microphone bias (micbias) generators are avail able, which provide a low noise reference for biasing electret condensor micr ophones (ecms) or for use as a low noise supply for digital microphones. digital volume control is available on all inputs (analogue and digital), with programmable ramp control for smooth, glitch-free operation. the in1l and in1r input signal paths and control r egisters are illustrated in figure 11. the in2 and in3 signal paths are equivalent to the in1 signal path. figure 11 input signal paths
production data WM5102 w pd, may 2013, rev 4.0 43 analogue microphone input up to six analogue microphones c an be connected to the WM5102, either in single-ended or differential mode. the applicable mode is selected using the in n _mode registers, as described later. note that the mode is configurable for each ster eo pair of inputs; the left and right channels of any pair of inputs are always in the same mode. the WM5102 includes external accessory detection circuits, which can det ect the presence of a microphone, and the status of a hookswitch or other push-buttons. when using th is function, it is recommended to use one of the right channel analogue microphone input paths, to ensure best immunity to electric al transients arising from the push-buttons. for single-ended input, the microphone si gnal is connected to the non-inverting input of the pgas (in n lp or in n rp). the inverting inputs of the pgas are connected to an internal reference in this configuration. for differential input, the non-inverted microphone signal is connected to the non-inverting input of the pgas (in n lp or in n rp), whilst the inverted (or ?noisy ground? ) signal is connected to the inverting input pins (in n ln or in n rn). the gain of the input pgas is contro lled via register settings, as defined in table 4. note that the input impedance of the analogue input paths is fixed across all pga gain settings. the analogue microphone input configurations ar e illustrated in figure 12 and figure 13. figure 12 single-ended microphone input figure 13 differential microphone input analogue line input line inputs can be connected to the WM5102 in a similar manner to the microphone inputs described above. single-ended and differential modes are supported on each of the six input paths. the applicable mode (single-ended or diffe rential) is selected using the in n _mode registers, as described later. note that the mode is configurabl e for each stereo pair of inputs; the left and right channels of any pair of inputs are always in the same mode. the analogue line input configurations are illustra ted in figure 14 and figure 15. note that the microphone bias (micbias) is not used for line input connections. figure 14 single-ended line input figure 15 differential line input
WM5102 production data w pd, may 2013, rev 4.0 44 digital microphone input up to six digital microphones can be connected to the WM5102. the digital microphone mode is selected using the in n _mode registers, as described later. no te that the mode is configurable for each stereo pair of inputs; the left and right channels of any pair of inputs are always in the same mode. in digital microphone mode, two channels of audio data are multiplexed on the dmicdat1, dmicdat2 or dmicdat3 pins. each of these ster eo interfaces is clock ed using the respective dmicclk1, dmicclk2 or dmicclk3 pin. when digital microphone input is enabled, the WM5102 outputs a clock signal on the applicable dmicclk n pin(s). the dmicclk n frequency is controlled by the respective in n _osr register, as described in table 1. see table 3 for details of the in n _osr registers. note that the dmicclkn frequencies noted in table 1 assume that the sysclk frequency is a multiple of 6.144mhz (sysclk_frac=0). if the sysclk frequency is a multiple of 5.6448mhz (sysclk_frac=1), then the dmicclkn frequencies will be scaled accordingly. condition dmicclkn frequency in n _osr = 00 1.536mhz in n _osr = 01 3.072mhz table 1 dmicclk frequency the voltage reference for each digital micr ophone interface is selectable, using the in n _dmic_sup registers. each interface may be referenced to micv dd, or to the micbias1, micbias2 or micbias3 levels. a pair of digital microphones is connected as illu strated in figure 16. the microphones must be configured to ensure that the left mic transmits a data bit when dmicclk is high, and the right mic transmits a data bit when dmicclk is low. t he WM5102 samples the digital microphone data at the end of each dmicclk phase. each microphone must tri-state its data output when the other microphone is transmitting. note that the WM5102 provides integrated pull-down resistors on the dmicdat1, dmicdat2 and dmicdat3 pins. this provides a flexible capability for interfacing with other devices. figure 16 digital microphone input
production data WM5102 w pd, may 2013, rev 4.0 45 two digital microphone channels are interleaved on dmicdat n . the digital microphone interface timing is illustrated in figure 17. each microphone must tri-state its data output when the other microphone is transmitting. figure 17 digital microphone interface timing when digital microphone input is enabled, the WM5102 outputs a clock signal on the applicable dmicclk pin(s). the dmicclk frequency is selectable, as described in table 1. note that sysclk must be present and enabled when using the digital microphone inputs; see ?clocking and sample rates? for details of sysc lk and the associated register control fields. input signal path enable the input signal paths are enabled usi ng the register bits described in table 2. the respective bit(s) must be enabled for analogue or digital input on the respective input path(s). the micvdd power domain must be enabled when us ing the analogue input signal path(s). this power domain is provided using an internal charge pump (cp2) and ldo regulator (ldo2). see ?charge pumps, regulators and voltage refer ence? for details of these circuits. the system clock, sysclk, must be confi gured and enabled before any audio path is enabled. the asyncclk and 32khz clock may also be requir ed, depending on the path configuration. see ?clocking and sample rates? for details of the system clocks. the WM5102 performs automatic checks to confir m that the sysclk frequency is high enough to support the input signal paths and associated adcs. if an attempt is made to enable an input signal path, and there are insufficient sysclk cycles to support it, then the attempt will be unsuccessful. (note that any signal paths that are already acti ve will not be affected under these circumstances.) the underclocked error condition c an be monitored using the gpio and/or interrupt functions. see ?general purpose input / output? and ?interrupts? for further details. the status bits in register r769 indicate t he status of each of the input signal paths. if an underclocked error condition occurs , then these bits provide readback of which input signal path(s) have been successfully enabled.
WM5102 production data w pd, may 2013, rev 4.0 46 register address bit label default description r768 (0300h) input enables 5 in3l_ena 0 input path 3 (left) enable 0 = disabled 1 = enabled 4 in3r_ena 0 input path 3 (right) enable 0 = disabled 1 = enabled 3 in2l_ena 0 input path 2 (left) enable 0 = disabled 1 = enabled 2 in2r_ena 0 input path 2 (right) enable 0 = disabled 1 = enabled 1 in1l_ena 0 input path 1 (left) enable 0 = disabled 1 = enabled 0 in1r_ena 0 input path 1 (right) enable 0 = disabled 1 = enabled r769 (0301h) input enables status 5 in3l_ena_sts 0 input path 3 (left) enable status 0 = disabled 1 = enabled 4 in3r_ena_sts 0 input path 3 (right) enable status 0 = disabled 1 = enabled 3 in2l_ena_sts 0 input path 2 (left) enable status 0 = disabled 1 = enabled 2 in2r_ena_sts 0 input path 2 (right) enable status 0 = disabled 1 = enabled 1 in1l_ena_sts 0 input path 1 (left) enable status 0 = disabled 1 = enabled 0 in1r_ena_sts 0 input path 1 (right) enable status 0 = disabled 1 = enabled table 2 input signal path enable input signal path sample rate control the input signal paths may be selected as input to the digital mixers or si gnal processing functions within the WM5102 digital core. the sample rate fo r the input signal paths is configured using the in_rate register - see table 20 within the ?digital core? section. note that sample rate conversion is required when routing the input signal paths to any signal chain that is asynchronous and/or configured for a different sample rate.
production data WM5102 w pd, may 2013, rev 4.0 47 input signal path configuration the WM5102 supports six input signal paths. each pair of inputs can be c onfigured as single-ended, differential, or digital microphone configuration. note that the mode is configurable for each stereo pair of inputs; the left and right channels of any pair of inputs are always in the same mode. the input signal path configurat ion is selected using the in n _mode registers (where ?n? identifies the associated input). the external circuit confi gurations are illustrated on the previous pages. the analogue input signal paths (singl e-ended or differential) each incor porate a pga to provide gain in the range 0db to +31db in 1db steps. note that these pgas do not provide pop suppression functions; it is recommended that the gain should not be adjusted whilst the re spective signal path is enabled. the analogue input pga gain is controlled using the in n l_pga_vol and in n r_pga_vol registers. note that separate volume control is provided for the left and right channels of each stereo pair. when the input signal path is c onfigured for digital microphone input, the voltage reference for the associated input/output pins is selectable using the in n _dmic_sup registers - each interface may be referenced to micvdd, or to the micbias1, micbias2 or micbias3 levels. a digital delay may be applied to any of the di gital microphone input channels. this feature can be used for phase adjustment of any digital input, incl uding directional control of multiple microphones. the delay is controlled using the innl_d mic_dly and innr_dmic_dly registers. the micvdd voltage is generated by an internal charge pump and ldo regulator. the micbias1, micbias2 and micbias3 outputs are derived from micvdd - see ?charge pumps, regulators and voltage reference?. under default register conditions, the input signal paths are confi gured for highest performance. this can be adjusted using the in n _osr registers, which provide control of the dmicclk n frequency and the adc oversample rate. the input signal paths are c onfigured using the register bits described in table 3. register address bit label default description r784 (0310h) in1l control 14:13 in1_osr [1:0] 01 input path 1 oversample rate when analogue input is selected (in1_mode=0x), this bit controls the performance mode 00 = low power mode 01 = high performance mode 1x = reserved when digital microphone input is selected (in1_mode=10), this bit controls the sample rate as below: 00 = 1.536mhz 01 = 3.072mhz 1x = reserved 12:11 in1_dmic_sup [1:0] 00 input path 1 dmic reference select (sets the dmicdat1 and dmicclk1 logic levels) 00 = micvdd 01 = micbias1 10 = micbias2 11 = micbias3 10:9 in1_mode [1:0] 00 input path 1 mode 00 = differential (in1xp - in1xn) 01 = single-ended (in1xp) 10 = digital microphone 11 = reserved
WM5102 production data w pd, may 2013, rev 4.0 48 register address bit label default description 7:1 in1l_pga_vol [6:0] 40h input path 1 (left) pga volume (applicable to analogue inputs only) 00h to 3fh = reserved 40h = 0db 41h = 1db 42h = 2db ? (1db steps) 5f = 31db 60h to 7fh = reserved r786 (0312h) dmic1l control 5:0 in1l_dmic_dly [5:0] 00h input path 1 (left) digital delay (applicable to digital input only) lsb = 1 sample, range is 0 to 63. (sample rate is controlled by in1_osr.) r788 (0314h) in1r control 7:1 in1r_pga_vol [6:0] 40h input path 1 (right) pga volume (applicable to analogue inputs only) 00h to 3fh = reserved 40h = 0db 41h = 1db 42h = 2db ? (1db steps) 5f = 31db 60h to 7fh = reserved r790 (0316h) dmic1r control 5:0 in1r_dmic_dly [5:0] 00h input path 1 (right) digital delay (applicable to digital input only) lsb = 1 sample, range is 0 to 63. (sample rate is controlled by in1_osr.) r792 (0318h) in2l control 14:13 in2_osr [1:0] 01 input path 2 oversample rate when analogue input is selected (in1_mode=0x), this bit controls the performance mode 00 = low power mode 01 = high performance mode 1x = reserved when digital microphone input is selected (in2_mode=10), this bit controls the sample rate as below: 00 = 1.536mhz 01 = 3.072mhz 1x = reserved 12:11 in2_dmic_sup [1:0] 00 input path 2 dmic reference select (sets the dmicdat2 and dmicclk2 logic levels) 00 = micvdd 01 = micbias1 10 = micbias2 11 = micbias3 10:9 in2_mode [1:0] 00 input path 2 mode 00 = differential (in2xp - in2xn) 01 = single-ended (in2xp) 10 = digital microphone 11 = reserved
production data WM5102 w pd, may 2013, rev 4.0 49 register address bit label default description 7:1 in2l_pga_vol [6:0] 40h input path 2 (left) pga volume (applicable to analogue inputs only) 00h to 3fh = reserved 40h = 0db 41h = 1db 42h = 2db ? (1db steps) 5f = 31db 60h to 7fh = reserved r794 (031ah) dmic2l control 5:0 in2l_dmic_dly [5:0] 00h input path 1 (left) digital delay (applicable to digital input only) lsb = 1 sample, range is 0 to 63. (sample rate is controlled by in2_osr.) r796 (031ch) in2r control 7:1 in2r_pga_vol [6:0] 40h input path 2 (right) pga volume (applicable to analogue inputs only) 00h to 3fh = reserved 40h = 0db 41h = 1db 42h = 2db ? (1db steps) 5f = 31db 60h to 7fh = reserved r798 (031eh) dmic2r control 5:0 in2r_dmic_dly [5:0] 00h input path 1 (right) digital delay (applicable to digital input only) lsb = 1 sample, range is 0 to 63. (sample rate is controlled by in2_osr.) r800 (0320h) in3l control 14:13 in3_osr [1:0] 01 input path 3 oversample rate when analogue input is selected (in1_mode=0x), this bit controls the performance mode 00 = low power mode 01 = high performance mode 1x = reserved when digital microphone input is selected (in3_mode=10), this bit controls the sample rate as below: 00 = 1.536mhz 01 = 3.072mhz 1x = reserved 12:11 in3_dmic_sup [1:0] 00 input path 3 dmic reference select (sets the dmicdat3 and dmicclk3 logic levels) 00 = micvdd 01 = micbias1 10 = micbias2 11 = micbias3 10:9 in3_mode [1:0] 00 input path 3 mode 00 = differential (in3xp - in3xn) 01 = single-ended (in3xp) 10 = digital microphone 11 = reserved
WM5102 production data w pd, may 2013, rev 4.0 50 register address bit label default description 7:1 in3l_pga_vol [6:0] 40h input path 3 (left) pga volume (applicable to analogue inputs only) 00h to 3fh = reserved 40h = 0db 41h = 1db 42h = 2db ? (1db steps) 5f = 31db 60h to 7fh = reserved r802 (0322h) dmic3l control 5:0 in3l_dmic_dly [5:0] 00h input path 1 (left) digital delay (applicable to digital input only) lsb = 1 sample, range is 0 to 63. (sample rate is controlled by in3_osr.) r804 (0324h) in3r control 7:1 in3r_pga_vol [6:0] 40h input path 3 (right) pga volume (applicable to analogue inputs only) 00h to 3fh = reserved 40h = 0db 41h = 1db 42h = 2db ? (1db steps) 5f = 31db 60h to 7fh = reserved r806 (0326h) dmic3r control 5:0 in3r_dmic_dly [5:0] 00h input path 1 (right) digital delay (applicable to digital input only) lsb = 1 sample, range is 0 to 63. (sample rate is controlled by in3_osr.) table 3 input signal path configuration input signal path digital volume control a digital volume control is provided on each of the input signal paths, providing -64db to +31.5db gain control in 0.5db steps. an independent mute contro l is also provided for each input signal path. whenever the gain or mute setting is changed, the signal path gain is ramped up or down to the new settings at a programmable rate. for increasing gai n (or un-mute), the rate is controlled by the in_vi_ramp register. for decreas ing gain (or mute), the rate is controlled by the in_vd_ramp register. note that the in_vi_ramp and in_v d_ramp registers should not be changed while a volume ramp is in progress. the in_vu bits control the loading of the input signal path digital volume and mute controls. when in_vu is set to 0, the digital volume and mute settings will be loaded into the respective control register, but will not actually change the signal path gain. the digital volume and mute settings on all of the input signal paths are updated when a 1 is wri tten to in_vu. this makes it possible to update the gain of multiple signal paths simultaneously. for correct gain ramp behaviour, the in_vu bits s hould not be written during the 0.75ms after any of the input path enable bits (see t able 2) have been asserted. it is recommended that the input path mute bit be set when the respective input path is enabled; the signal path can then be un-muted after the 0.75ms has elapsed. note that, although the digital volume control regi sters provide 0.5db steps, the internal circuits provide signal gain adjustment in 0.125db steps. this allows a very high degree of gain control, and smooth volume ramping under all operating conditions. the digital volume control register fiel ds are described in table 4 and table 5.
production data WM5102 w pd, may 2013, rev 4.0 51 register address bit label default description r777 (0309h) input volume ramp 6:4 in_vd_ramp [2:0] 010 input volume decreasing ramp rate (seconds/6db) 000 = 0ms 001 = 0.5ms 010 = 1ms 011 = 2ms 100 = 4ms 101 = 8ms 110 = 15ms 111 = 30ms this register should not be changed while a volume ramp is in progress. 2:0 in_vi_ramp [2:0] 010 input volume increasing ramp rate (seconds/6db) 000 = 0ms 001 = 0.5ms 010 = 1ms 011 = 2ms 100 = 4ms 101 = 8ms 110 = 15ms 111 = 30ms this register should not be changed while a volume ramp is in progress. r785 (0311h) adc digital volume 1l 9 in_vu input signal paths volume and mute update writing a 1 to this bit will cause the input signal paths volume and mute settings to be updated simultaneously 8 in1l_mute 1 input path 1 (left) digital mute 0 = un-mute 1 = mute 7:0 in1l_vol [7:0] 80h input path 1 (left) digital volume -64db to +31.5db in 0.5db steps 00h = -64db 01h = -63.5db ? (0.5db steps) 80h = 0db ? (0.5db steps) bfh = +31.5db c0h to ffh = reserved (see table 5 for volume range) r789 (0315h) adc digital volume 1r 9 in_vu input signal paths volume and mute update writing a 1 to this bit will cause the input signal paths volume and mute settings to be updated simultaneously 8 in1r_mute 1 input path 1 (right) digital mute 0 = un-mute 1 = mute
WM5102 production data w pd, may 2013, rev 4.0 52 register address bit label default description 7:0 in1r_vol [7:0] 80h input path 1 (right) digital volume -64db to +31.5db in 0.5db steps 00h = -64db 01h = -63.5db ? (0.5db steps) 80h = 0db ? (0.5db steps) bfh = +31.5db c0h to ffh = reserved (see table 5 for volume range) r793 (0319h) adc digital volume 2l 9 in_vu input signal paths volume and mute update writing a 1 to this bit will cause the input signal paths volume and mute settings to be updated simultaneously 8 in2l_mute 1 input path 2 (left) digital mute 0 = un-mute 1 = mute 7:0 in2l_vol [7:0] 80h input path 2 (left) digital volume -64db to +31.5db in 0.5db steps 00h = -64db 01h = -63.5db ? (0.5db steps) 80h = 0db ? (0.5db steps) bfh = +31.5db c0h to ffh = reserved (see table 5 for volume range) r797 (031dh) adc digital volume 2r 9 in_vu input signal paths volume and mute update writing a 1 to this bit will cause the input signal paths volume and mute settings to be updated simultaneously 8 in2r_mute 1 input path 2 (right) digital mute 0 = un-mute 1 = mute 7:0 in2r_vol [7:0] 80h input path 2 (right) digital volume -64db to +31.5db in 0.5db steps 00h = -64db 01h = -63.5db ? (0.5db steps) 80h = 0db ? (0.5db steps) bfh = +31.5db c0h to ffh = reserved (see table 5 for volume range) r801 (0321h) adc digital volume 3l 9 in_vu input signal paths volume and mute update writing a 1 to this bit will cause the input signal paths volume and mute settings to be updated simultaneously 8 in3l_mute 1 input path 3 (left) digital mute 0 = un-mute 1 = mute
production data WM5102 w pd, may 2013, rev 4.0 53 register address bit label default description 7:0 in3l_vol [7:0] 80h input path 3 (left) digital volume -64db to +31.5db in 0.5db steps 00h = -64db 01h = -63.5db ? (0.5db steps) 80h = 0db ? (0.5db steps) bfh = +31.5db c0h to ffh = reserved (see table 5 for volume range) r805 (0325h) adc digital volume 3r 9 in_vu input signal paths volume and mute update writing a 1 to this bit will cause the input signal paths volume and mute settings to be updated simultaneously 8 in3r_mute 1 input path 3 (right) digital mute 0 = un-mute 1 = mute 7:0 in3r_vol [7:0] 80h input path 3 (right) digital volume -64db to +31.5db in 0.5db steps 00h = -64db 01h = -63.5db ? (0.5db steps) 80h = 0db ? (0.5db steps) bfh = +31.5db c0h to ffh = reserved (see table 5 for volume range) table 4 input signal path digital volume control
WM5102 production data w pd, may 2013, rev 4.0 54 input volume register v olume (db) input volume register v olume (db) input volume register v olume (db) input volume register v olume (db) 00h -64.0 40h -32.0 80h 0.0 c0h reserved 01h -63.5 41h -31.5 81h 0.5 c1h reserved 02h -63.0 42h -31.0 82h 1.0 c2h reserved 03h -62.5 43h -30.5 83h 1.5 c3h reserved 04h -62.0 44h -30.0 84h 2.0 c4h reserved 05h -61.5 45h -29.5 85h 2.5 c5h reserved 06h -61.0 46h -29.0 86h 3.0 c6h reserved 07h -60.5 47h -28.5 87h 3.5 c7h reserved 08h -60.0 48h -28.0 88h 4.0 c8h reserved 09h -59.5 49h -27.5 89h 4.5 c9h reserved 0ah -59.0 4ah -27.0 8ah 5.0 cah reserved 0bh -58.5 4bh -26.5 8bh 5.5 cbh reserved 0ch -58.0 4ch -26.0 8ch 6.0 cch reserved 0dh -57.5 4dh -25.5 8dh 6.5 cdh reserved 0eh -57.0 4eh -25.0 8eh 7.0 ceh reserved 0fh -56.5 4fh -24.5 8fh 7.5 cfh reserved 10h -56.0 50h -24.0 90h 8.0 d0h reserved 11h -55.5 51h -23.5 91h 8.5 d1h reserved 12h -55.0 52h -23.0 92h 9.0 d2h reserved 13h -54.5 53h -22.5 93h 9.5 d3h reserved 14h -54.0 54h -22.0 94h 10.0 d4h reserved 15h -53.5 55h -21.5 95h 10.5 d5h reserved 16h -53.0 56h -21.0 96h 11.0 d6h reserved 17h -52.5 57h -20.5 97h 11.5 d7h reserved 18h -52.0 58h -20.0 98h 12.0 d8h reserved 19h -51.5 59h -19.5 99h 12.5 d9h reserved 1ah -51.0 5ah -19.0 9ah 13.0 dah reserved 1bh -50.5 5bh -18.5 9bh 13.5 dbh reserved 1ch -50.0 5ch -18.0 9ch 14.0 dch reserved 1dh -49.5 5dh -17.5 9dh 14.5 ddh reserved 1eh -49.0 5eh -17.0 9eh 15.0 deh reserved 1fh -48.5 5fh -16.5 9fh 15.5 dfh reserved 20h -48.0 60h -16.0 a0h 16.0 e0h reserved 21h -47.5 61h -15.5 a1h 16.5 e1h reserved 22h -47.0 62h -15.0 a2h 17.0 e2h reserved 23h -46.5 63h -14.5 a3h 17.5 e3h reserved 24h -46.0 64h -14.0 a4h 18.0 e4h reserved 25h -45.5 65h -13.5 a5h 18.5 e5h reserved 26h -45.0 66h -13.0 a6h 19.0 e6h reserved 27h -44.5 67h -12.5 a7h 19.5 e7h reserved 28h -44.0 68h -12.0 a8h 20.0 e8h reserved 29h -43.5 69h -11.5 a9h 20.5 e9h reserved 2ah -43.0 6ah -11.0 aah 21.0 eah reserved 2bh -42.5 6bh -10.5 abh 21.5 ebh reserved 2ch -42.0 6ch -10.0 ach 22.0 ech reserved 2dh -41.5 6dh -9.5 adh 22.5 edh reserved 2eh -41.0 6eh -9.0 aeh 23.0 eeh reserved 2fh -40.5 6fh -8.5 afh 23.5 efh reserved 30h -40.0 70h -8.0 b0h 24.0 f0h reserved 31h -39.5 71h -7.5 b1h 24.5 f1h reserved 32h -39.0 72h -7.0 b2h 25.0 f2h reserved 33h -38.5 73h -6.5 b3h 25.5 f3h reserved 34h -38.0 74h -6.0 b4h 26.0 f4h reserved 35h -37.5 75h -5.5 b5h 26.5 f5h reserved 36h -37.0 76h -5.0 b6h 27.0 f6h reserved 37h -36.5 77h -4.5 b7h 27.5 f7h reserved 38h -36.0 78h -4.0 b8h 28.0 f8h reserved 39h -35.5 79h -3.5 b9h 28.5 f9h reserved 3ah -35.0 7ah -3.0 bah 29.0 fah reserved 3bh -34.5 7bh -2.5 bbh 29.5 fbh reserved 3ch -34.0 7ch -2.0 bch 30.0 fch reserved 3dh -33.5 7dh -1.5 bdh 30.5 fdh reserved 3eh -33.0 7eh -1.0 beh 31.0 feh reserved 00. -32.5 7fh -0.5 bfh 31.5 ffh reserved table 5 input signal path digital volume range
production data WM5102 w pd, may 2013, rev 4.0 55 digital microphone interface pull-down the WM5102 provides integrated pull-down resist ors on the dmicdat1, dmicdat2 and dmicdat3 pins. this provides a flexible capabilit y for interfacing with other devices. each of the pull-down resistors can be configured independently using the register bits described in table 6. note that, if the dmicdat1, dmicdat2 or dmicdat3 digital microphone input paths are disabled, then the pull-down will be disabled on the respective pin. register address bit label default description r3106 (0c22h) misc pad ctrl 3 2 dmicdat3_pd 0 dmicdat3 pull-down control 0 = disabled 1 = enabled 1 dmicdat2_pd 0 dmicdat2 pull-down control 0 = disabled 1 = enabled 0 dmicdat1_pd 0 dmicdat1 pull-down control 0 = disabled 1 = enabled table 6 digital microphone interface pull-down control
WM5102 production data w pd, may 2013, rev 4.0 56 digital core the WM5102 digital core provides extensive mixing and processing capabilities for multiple signal paths. the configuration is highly flexible, and virtually every conc eivable input/out put connection can be supported between the available processing blocks. the digital core provides param etric equalisation (eq) functions, dynamic range control (drc), low- pass / high-pass filters (lhpf), and programmable dsp capability. the dsp can support functions such as wind noise, side-tone or other progra mmable filters, also dynamic range control and compression, or virtual surround sound and other audio enhancements. the WM5102 supports multiple signal paths through t he digital core. stereo full-duplex sample rate conversion is provided to allow digital audio to be routed between input (adc) paths, output (dac) paths, digital audio interfaces (aif1, aif2 and ai f3) and slimbus paths operating at different sample rates and/or referenced to asynchronous clock domains. the dsp functions are highly progr ammable, using application-specif ic control sequences. it should be noted that the dsp configuration data is lost whenever the dcvdd power domain is removed; the dsp configuration data must be downloaded to t he WM5102 each time the device is powered up. the procedure for configuring the WM5102 dsp functions is tailored to each customer?s application; please contact your local wolfson representative for more details. the WM5102 incorporates two 1khz tone generators which can be used for ? beep? functions through any of the audio signal paths. a white noise generator is incorporated, to provide ?comfort noise? in cases where silence (digital mute) is not desirable. a haptic signal generator is provided, for use with external haptic devices ( eg. mechanical vibration actuators). two pulse width modulation (pwm) signal generators are also provided; the pwm waveforms can be modulated by an audio source with in the digital core, and can be output on a gpio pin. an overview of the digital core processing and mixi ng functions is provided in figure 18. an overview of the external digital interfac e paths is provided in figure 19. the control registers associated with the digital core signal paths are shown in figure 20 through to figure 37. the full list of digital mixer control regi sters is provided in the ?register map? section (register r1600 through to r2920). generic regist er definitions are provided in table 7.
production data WM5102 w pd, may 2013, rev 4.0 57 figure 18 digital core - internal signal processing
WM5102 production data w pd, may 2013, rev 4.0 58 + aif3 tx2 output + aif3 tx1 output aif3 rx1 (30h) aif3 rx2 (31h) + aif2 tx2 output + aif2 tx1 output aif2 rx1 (28h) aif2 rx2 (29h) + aif1 tx8 output + aif1 tx7 output + aif1 tx6 output + aif1 tx5 output + aif1 tx4 output + aif1 tx3 output + aif1 tx2 output + aif1 tx1 output aif1 rx3 (22h) aif1 rx4 (23h) aif1 rx5 (24h) aif1 rx6 (25h) aif1 rx7 (26h) aif1 rx8 (27h) aif1 rx1 (20h) aif1 rx2 (21h) + slimbus tx8 output + slimbus tx7 output + slimbus tx6 output + slimbus tx5 output + slimbus tx4 output + slimbus tx3 output + slimbus tx2 output + slimbus tx1 output slimbus rx3 (3ah) slimbus rx4 (3bh) slimbus rx5 (3ch) slimbus rx6 (3dh) slimbus rx7 (3eh) slimbus rx8 (3fh) slimbus rx1 (38h) slimbus rx2 (39h) out5r output + out5l output + out4r output + out4l output + out3 output + + out2r output + out2l output + out1r output + out1l output figure 19 digital core - external digital interfaces digital core mixers the WM5102 provides an extensive di gital mixing capability. the digital core signal processing blocks and audio interface paths are illustrated in figure 18 and figure 19. a 4-input digital mixer is associated with many of these functions, as illustrated. the digital mixer circuit is identical in each in stance, providing up to 4 selectable input sources, with independent volume control on each input. the control registers associated with the digital core signal paths are shown in figure 20 through to figure 37. the full list of digital mixer control regi sters is provided in the ?register map? section (register r1600 through to r2920). further description of the associated control register s is provided below. generic register definitions are provided in table 7. the digital mixer input sources are selected using the associated *_src n registers; the volume control is implemented via the associated *_vol n registers. the asrc, isrc, and dsp aux input functions support selectable input sources, but do not
production data WM5102 w pd, may 2013, rev 4.0 59 incorporate any digital mixing. t he respective input source (*_src n ) registers are identical to those of the digital mixers. the *_src n registers select the input source(s) for the respective mixer or si gnal processing block. note that the selected input source(s) must be confi gured for the same sample rate as the block(s) to which they are connected. sample rate conversi on functions are availabl e to support flexible interconnectivity - see ?asynchronous sample ra te converter (asrc)? and ?isochronous sample rate converter (isrc)?. a status bit associated with each of the conf igurable input sources provides readback for the respective signal path. if an under clocked error condition occurs, t hen these bits provide readback of which signal path(s) have been successfully enabled. the generic register definition for the di gital mixers is provided in table 7. register address bit label default description r1600 (0640h) to r2920 (0b68h) 15 *_stsn valid for every digital core function input (digital mixers, dsp aux inputs, asrc & isrc inputs). 0 [digital core function] input n status 0 = disabled 1 = enabled 7:1 *_voln valid for every digital mixer input. 40h [digital code mixer] input n volume -32db to +16db in 1db steps 00h to 20h = -32db 21h = -31db 22h = -30db ... (1db steps) 40h = 0db ... (1db steps) 50h = +16db 51h to 7fh = +16db 8:0 *_srcn valid for every digital core function input (digital mixers, dsp aux inputs, asrc & isrc inputs). 00h [digital core function] input n source select 00h = silence (mute) 04h = tone generator 1 05h = tone generator 2 06h = haptic generator 08h = aec loopback 0ch = mic mute mixer 0dh = noise generator 10h = in1l signal path 11h = in1r signal path 12h = in2l signal path 13h = in2r signal path 14h = in3l signal path 15h = in3r signal path 20h = aif1 rx1 21h = aif1 rx2 22h = aif1 rx3 23h = aif1 rx4 24h = aif1 rx5 25h = aif1 rx6 26h = aif1 rx7 27h = aif1 rx8
WM5102 production data w pd, may 2013, rev 4.0 60 register address bit label default description 28h = aif2 rx1 29h = aif2 rx2 30h = aif3 rx1 31h = aif3 rx2 38h = slimbus rx1 39h = slimbus rx2 3ah = slimbus rx3 3bh = slimbus rx4 3ch = slimbus rx5 3dh = slimbus rx6 3eh = slimbus rx7 3fh = slimbus rx8 50h = eq1 51h = eq2 52h = eq3 53h = eq4 58h = drc1 left 59h = drc1 right 60h = lhpf1 61h = lhpf2 62h = lhpf3 63h = lhpf4 68h = dsp1 channel 1 69h = dsp1 channel 2 6ah = dsp1 channel 3 6bh = dsp1 channel 4 6ch = dsp1 channel 5 6dh = dsp1 channel 6 90h = asrc1 left 91h = asrc1 right 92h = asrc2 left 93h = asrc2 right a0h = isrc1 int1 a1h = isrc1 int2 a4h = isrc1 dec1 a5h = isrc1 dec2 a8h = isrc2 int1 a9h = isrc2 int2 ach = isrc2 dec1 adh = isrc2 dec2 table 7 digital core mixer control registers
production data WM5102 w pd, may 2013, rev 4.0 61 digital core inputs the digital core comprises multiple input paths as illustrated in figure 20. any of these inputs may be selected as a source to the digital mixers or signal processing functions within the WM5102 digital core. note that the outputs from other blocks within the digital core may also be selected as input to the digital mixers or signal processi ng functions within the WM5102 digi tal core. those input sources, which are not shown in figure 20, are described separ ately in other sections of the ?digital core? description. the bracketed numbers in figure 20, eg. ?(10h)? indicate the corresponding *_src n register setting for selection of that signal as an i nput to another digital core function. the sample rate for the input signal paths is c onfigured using the applicable in_rate, aifn_rate or slimrxn_rate register - see table 20. note that sample rate conversion is required when routing the input signal paths to any signal chain that is asynchronous and/or configured for a different sample rate. figure 20 digital core inputs
WM5102 production data w pd, may 2013, rev 4.0 62 digital core output mixers the digital core comprises multiple output paths . the output paths associated with aif1, aif2 and aif3 are illustrated in figure 21. the output paths associated with out1, out2, out3, out4 and out5 are illustrated in figure 22. the output paths associated with the slimbus interface are illustrated in figure 23. a 4-input mixer is associated with each output. t he 4 input sources are selectable in each case, and independent volume control is provided for each path. the aif1, aif2 and aif3 output mixer control regi sters (see figure 21) are located at register addresses r1792 (700h) through to r1935 (78fh). the out1, out2, out3, out4 and out5 output mixer control registers (see figure 22) are lo cated at addresses r1664 (680h) through to r1743 (06cfh). the slimbus output mixer control regist ers (see figure 23) are located at addresses r1984 (7c0h) through to r2047 (7ffh). the full list of digital mixer control registers is pr ovided in the ?register map? section (register r1600 through to r2920). generic register def initions are provided in table 7. the *_src n registers select the input source(s) for the re spective mixers. note that the selected input source(s) must be configured for the same sample rate as the mixer to which they are connected. sample rate conversion functi ons are available to support fl exible interconnectivity - see ?asynchronous sample rate converter (asrc)? and ?isochronous sample rate converter (isrc)?. the sample rate for the output signal paths is configured using t he applicable out_rate, aifn_rate or slimtxn_rate register - see table 20. note that sample rate conversion is required when routing the output signal paths to any signal c hain that is asynchronous and/or configured for a different sample rate. the WM5102 performs automatic checks to confir m that the sysclk frequency is high enough to support the output mixer paths. if an attempt is made to enable an output mixer path, and there are insufficient sysclk cycles to support it, then the attempt will be unsuccessful. (note that any signal paths that are already active will not be affected under these circumstances.) the underclocked error condition c an be monitored using the gpio and/or interrupt functions. see ?general purpose input / output? and ?interrupts? for further details. the status bits in registers r1600 to r2920 indicate the status of each of the digital mixers. if an underclocked error condition occu rs, then these bits provide r eadback of which mixer(s) have been successfully enabled.
production data WM5102 w pd, may 2013, rev 4.0 63 figure 21 digital core aif outputs
WM5102 production data w pd, may 2013, rev 4.0 64 figure 22 digital core outn outputs
production data WM5102 w pd, may 2013, rev 4.0 65 figure 23 digital core slimbus outputs mic mute mixer the mic mute mixer function suppor ts applications where two signal paths are multiplexed into a single output. a typical use case is muting a microphone audio path and inserting a ?comfort noise? signal in place of the normal audio path. the mic mute mixer function comprises two digital mixers (micmix and noisemix), as illustrated in figure 24. a multiplexer selects one or other mixer as the mic mute output signal. up to 4 input sources can be selected for each mixer, and independent volume control is provided for each path. figure 24 mic mute digital mixers
WM5102 production data w pd, may 2013, rev 4.0 66 the micmix and noisemix control registers (see fi gure 24) are located at register addresses r1632 (0660h) through to r1647 (066fh). the full list of digital mixer control registers is pr ovided in the ?register map? section (register r1600 through to r2920). generic register def initions are provided in table 7. the mic mute mixer can be selected as input to any of the digital mixers or signal processing functions within the WM5102 digital core. the bracketed num ber (0ch) in figure 24 indicates the corresponding *_src n register setting for selection of the mic mute mi xer as an input to another digital core function. the sample rate for the mic mute mixer and mult iplexer is configured using the micmute_rate register - see table 20. note that sample rate c onversion is required when routing the mic mute mixer to any signal chain that is asynchronous and/ or configured for a different sample rate. the control registers associated with the mic mute mixer function are described in table 8. the output of the mic mute mixer and multiplexer is enabled using micmute_mix_ena. the multiplexer is controlled using the micmute_ noise_ena register bit, selecting micmix or noisemix as the output signal source. under recommended operating conditions, the micm ix output is selected for normal (audio) conditions, and the noisemix output is selected for mute (or ?comfort noise?) conditions. register address bit label default description r707 (02c3h) mic noise mix control 1 7 micmute_nois e_ena 0 mic mute mixer control 0 = mic mix 1 = noise mix 6 micmute_mix_e na 0 mic mute mixer enable 0 = disabled 1 = enabled table 8 mic mute mixer control registers the WM5102 performs automatic checks to confir m that the sysclk frequency is high enough to support the commanded digital mixi ng functions. if an attempt is made to enable a micmix or noisemix signal path, and there are insufficient sysc lk cycles to support it, then the attempt will be unsuccessful. (note that any signal paths that ar e already active will not be affected under these circumstances.) the underclocked error condition c an be monitored using the gpio and/or interrupt functions. see ?general purpose input / output? and ?interrupts? for further details. the status bits in registers r1600 to r2920 indicate the status of each of the digital mixers. if an underclocked error condition occu rs, then these bits provide r eadback of which mixer(s) have been successfully enabled, and which mixer(s) could not be enabled. 5-band parametric equaliser (eq) the digital core provides four eq processing blocks as illustrated in figure 25. a 4-input mixer is associated with each eq. the 4 input sources are selectable in each case, and independent volume control is provided for each path. each eq block supports 1 output. the eq provides selective control of 5 frequency bands as described below. the low frequency band (band 1) filter can be configured ei ther as a peak filter or a shelving filter. when configured as a shelving filt er, is provides adjustable gain below the band 1 cut-off frequency. as a peak filter, it provides adjustable gain within a defined fr equency band that is centred on the band 1 frequency. the mid frequency bands (band 2, band 3, band 4) filt ers are peak filters, which provide adjustable gain around the respective centre frequency.
production data WM5102 w pd, may 2013, rev 4.0 67 the high frequency band (band 5) filter is a shelving filter, which provides adjustable gain above the band 5 cut-off frequency. figure 25 digital core eq b locks the eq1, eq2, eq3 and eq4 mixer control regist ers (see figure 25) are located at register addresses r2176 (880h) through to r2207 (89fh). the full list of digital mixer control registers is pr ovided in the ?register map? section (register r1600 through to r2920). generic register def initions are provided in table 7. the *_src n registers select the input source(s) for the respective eq processing blocks. note that the selected input source(s) must be configured for the same sample rate as the eq to which they are connected. sample rate conversion functions are available to support flexible interconnectivity - see ?asynchronous sample rate converter (asrc)? and ?isochronous sample rate converter (isrc)?. the bracketed numbers in figure 25, eg. ?(50h)? indicate the corresponding *_src n register setting for selection of that signal as an i nput to another digital core function. the sample rate for the eq function is configured using the fx_rate register - see table 20. note that the eq, drc and lhpf functions must all be configured for the same sample rate. sample rate conversion is required when routi ng the eq signal paths to any si gnal chain that is asynchronous and/or configured for a different sample rate. the control registers associated with the eq functions are described in table 10. the cut-off or centre frequencies for the 5-band eq ar e set using the coefficients held in the registers identified in table 9. these coefficients are der ived using tools provided in wolfson?s wisce? evaluation board control software; pl ease contact your local wolfson representative for more details. eq register addresses eq1 r3602 (0e10h) to r3620 (0e24h) eq2 r3624 (0e28h) to r3642 (0e3ah) eq3 r3646 (0e3eh) to r3664 (0e53h) eq4 r3668 (0e54h) to r3686 (0e66h) table 9 eq coefficient registers
WM5102 production data w pd, may 2013, rev 4.0 68 register address bit label default description r3585 (0e01h) fx_ctrl2 15:4 fx_sts [11:0] 000h lhpf, drc, eq enable status indicates the status of each of the respective signal pr ocessing functions. [11] = eq4 [10] = eq3 [9] = eq2 [8] = eq1 [7] = reserved [6] = reserved [5] = drc1 (right) [4] = drc1 (left) [3] = lhpf4 [2] = lhpf3 [1] = lhpf2 [0] = lhpf1 each bit is coded as: 0 = disabled 1 = enabled r3600 (0e10h) eq1_1 15:11 eq1_b1_gain [4:0] 01100 eq1 band 1 gain -12db to +12db in 1db steps (see table 11 for gain range) 10:6 eq1_b2_gain [4:0] 01100 eq1 band 2 gain -12db to +12db in 1db steps (see table 11 for gain range) 5:1 eq1_b3_gain [4:0] 01100 eq1 band 3 gain -12db to +12db in 1db steps (see table 11 for gain range) 0 eq1_ena 0 eq1 enable 0 = disabled 1 = enabled r3601 (0e11h) eq1_2 15:11 eq1_b4_gain [4:0] 01100 eq1 band 4 gain -12db to +12db in 1db steps (see table 11 for gain range) 10:6 eq1_b5_gain [4:0] 01100 eq1 band 5 gain -12db to +12db in 1db steps (see table 11 for gain range) 0 eq1_b1_mode 0 eq1 band 1 mode 0 = shelving filter 1 = peak filter r3602 (0e12h) to r3620 (e24h) 15:0 eq1_b1_* eq1_b2_* eq1_b3_* eq1_b4_* eq1_b5_* eq1 frequency coefficients refer to wisce evaluation board control software for the deriviation of these field values. r3622 (0e26h) eq2_1 15:11 eq2_b1_gain [4:0] 01100 eq2 band 1 gain -12db to +12db in 1db steps (see table 11 for gain range) 10:6 eq2_b2_gain [4:0] 01100 eq2 band 2 gain -12db to +12db in 1db steps (see table 11 for gain range) 5:1 eq2_b3_gain [4:0] 01100 eq2 band 3 gain -12db to +12db in 1db steps (see table 11 for gain range)
production data WM5102 w pd, may 2013, rev 4.0 69 register address bit label default description 0 eq2_ena 0 eq2 enable 0 = disabled 1 = enabled r3623 (0e27h) eq2_2 15:11 eq2_b4_gain [4:0] 01100 eq2 band 4 gain -12db to +12db in 1db steps (see table 11 for gain range) 10:6 eq2_b5_gain [4:0] 01100 eq2 band 5 gain -12db to +12db in 1db steps (see table 11 for gain range) 0 eq2_b1_mode 0 eq2 band 1 mode 0 = shelving filter 1 = peak filter r3624 (0e28h) to r3642 (e3ah) 15:0 eq2_b1_* eq2_b2_* eq2_b3_* eq2_b4_* eq2_b5_* eq2 frequency coefficients refer to wisce evaluation board control software for the deriviation of these field values. r3644 (0e3ch) eq3_1 15:11 eq3_b1_gain [4:0] 01100 eq3 band 1 gain -12db to +12db in 1db steps (see table 11 for gain range) 10:6 eq3_b2_gain [4:0] 01100 eq3 band 2 gain -12db to +12db in 1db steps (see table 11 for gain range) 5:1 eq3_b3_gain [4:0] 01100 eq3 band 3 gain -12db to +12db in 1db steps (see table 11 for gain range) 0 eq3_ena 0 eq3 enable 0 = disabled 1 = enabled r3645 (0e3dh) eq3_2 15:11 eq3_b4_gain [4:0] 01100 eq3 band 4 gain -12db to +12db in 1db steps (see table 11 for gain range) 10:6 eq3_b5_gain [4:0] 01100 eq3 band 5 gain -12db to +12db in 1db steps (see table 11 for gain range) 0 eq3_b1_mode 0 eq3 band 1 mode 0 = shelving filter 1 = peak filter r3646 (0e3eh) to r3664 (e50h) 15:0 eq3_b1_* eq3_b2_* eq3_b3_* eq3_b4_* eq3_b5_* eq3 frequency coefficients refer to wisce evaluation board control software for the deriviation of these field values. r3666 (0e52h) eq4_1 15:11 eq4_b1_gain [4:0] 01100 eq4 band 1 gain -12db to +12db in 1db steps (see table 11 for gain range) 10:6 eq4_b2_gain [4:0] 01100 eq4 band 2 gain -12db to +12db in 1db steps (see table 11 for gain range) 5:1 eq4_b3_gain [4:0] 01100 eq4 band 3 gain -12db to +12db in 1db steps (see table 11 for gain range)
WM5102 production data w pd, may 2013, rev 4.0 70 register address bit label default description 0 eq4_ena 0 eq4 enable 0 = disabled 1 = enabled r3667 (0e53h) eq4_2 15:11 eq4_b4_gain [4:0] 01100 eq4 band 4 gain -12db to +12db in 1db steps (see table 11 for gain range) 10:6 eq4_b5_gain [4:0] 01100 eq4 band 5 gain -12db to +12db in 1db steps (see table 11 for gain range) 0 eq4_b1_mode 0 eq4 band 1 mode 0 = shelving filter 1 = peak filter r3668 (0e54h) to r3686 (e66h) 15:0 eq4_b1_* eq4_b2_* eq4_b3_* eq4_b4_* eq4_b5_* eq4 frequency coefficients refer to wisce evaluation board control software for the deriviation of these field values. table 10 eq enable and gain control eq gain setting gain (db) 00000 -12 00001 -11 00010 -10 00011 -9 00100 -8 00101 -7 00110 -6 00111 -5 01000 -4 01001 -3 01010 -2 01011 -1 01100 0 01101 +1 01110 +2 01111 +3 10000 +4 10001 +5 10010 +6 10011 +7 10100 +8 10101 +9 10110 +10 10111 +11 11000 +12 11001 to 11111 reserved table 11 eq gain control range
production data WM5102 w pd, may 2013, rev 4.0 71 the WM5102 performs automatic checks to confir m that the sysclk frequency is high enough to support the commanded eq and digital mixing functions . if an attempt is made to enable an eq signal path, and there are insufficient sysclk cycles to support it, then the attempt will be unsuccessful. (note that any signal paths that are already acti ve will not be affected under these circumstances.) the underclocked error can be moni tored using the gpio and/or in terrupt functions. see ?general purpose input / output? and ?interrupts? for further details. the fx_sts field in register r3585 indicates t he status of each of the eq, drc and lhpf signal paths. if an underclocked error condi tion occurs, then this register provides readback of which eq, drc or lhpf signal path(s) have been successfully enabled. the status bits in registers r1600 to r2920 indicate the status of each of the digital mixers. if an underclocked error condition occu rs, then these bits provide r eadback of which mixer(s) have been successfully enabled. dynamic range control (drc) the digital core provides a stereo dynamic range control (drc) processing block as illustrated in figure 26. a 4-input mixer is associated with each drc input channel. the 4 input sources are selectable in each case, and independent volume control is provided for each path. the function of the drc is to adjust the signal gai n in conditions where the input amplitude is unknown or varies over a wide range, e.g. when recording from microphones built into a handheld system, or to restrict the dynamic range of an output signal path. the drc can apply compression and automatic level cont rol to the signal path. it incorporates ?anti- clip? and ?quick release? features for handling transients in order to improve intelligibility in the presence of loud impulsive noises. the drc also incorporates a noise gate function, which provides additional attenuation of very low- level input signals. this means that the signal path is quiet when no signal is present, giving an improvement in background noise level under these conditions. a signal detect function is provided within the drc; this can be used to detect the presence of an audio signal, and used to trigger other events. the si gnal detect function can be used as an interrupt event, or as a gpio output, or used to trigger the control write sequencer.
WM5102 production data w pd, may 2013, rev 4.0 72 figure 26 dynamic range control (drc) block the drc1 mixer control registers (see figure 26) are located at register addresses r2240 (8c0h) through to r2255 (08cfh). the full list of digital mixer control registers is pr ovided in the ?register map? section (register r1600 through to r2920). generic register def initions are provided in table 7. the *_src n registers select the input source(s) for t he respective drc processing blocks. note that the selected input source(s) must be configured for the same sample rate as the drc to which they are connected. sample rate conver sion functions are available to s upport flexible interconnectivity - see ?asynchronous sample rate converter (as rc)? and ?isochronous sample rate converter (isrc)?. the bracketed numbers in figure 26, eg. ?(58h)? indicate the corresponding *_src n register setting for selection of that signal as an i nput to another digital core function. the sample rate for the drc function is configured using the fx_rate register - see table 20. note that the eq, drc and lhpf functions must all be configured for the same sample rate. sample rate conversion is required when routi ng the drc signal paths to any signal chain that is asynchronous and/or configured for a different sample rate. the drc functions are enabled us ing the control registers described in table 12.
production data WM5102 w pd, may 2013, rev 4.0 73 register address bit label default description r3712 (0e80h) drc1 ctrl1 1 drc1l_ena 0 drc1 (left) enable 0 = disabled 1 = enabled 0 drc1r_ena 0 drc1 (right) enable 0 = disabled 1 = enabled table 12 drc enable drc compression / expansion / limiting the drc supports two different compression regions , separated by a ?knee? at a specific input amplitude. in the region above the knee, the compression slope drc1_hi_comp applies; in the region below the knee, the compression slope drc1_lo_comp applies. the drc also supports a noise gate region, where lo w-level input signals are heavily attenuated. this function can be enabled or disabled according to the application requirements. the drc response in this region is defined by the expansion slope drc1_ng_exp. for additional attenuation of signals in the noise gate region, an additional ?knee? can be defined (shown as ?knee2? in figure 27). when this knee is enabled, this introduces an infinitely steep drop- off in the drc response pattern between the drc1_lo_comp and drc1_ng_exp regions. the overall drc compression characteristic in ?steady state? (i.e. where the input amplitude is near- constant) is illustrated in figure 27. figure 27 drc response characteristic the slope of the drc response is determined by register fields drc1_hi_comp and drc1_lo_comp. a slope of 1 indicates constant gai n in this region. a slope less than 1 represents compression (i.e. a change in input amplitude produc es only a smaller change in output amplitude). a slope of 0 indicates that the target output amplit ude is the same across a range of input amplitudes; this is infinite compression. when the noise gate is enabled, the drc respons e in this region is determined by the drc1_ng_exp register. a slope of 1 indicates const ant gain in this region. a slope greater than 1 represents expansion (ie. a change in input amplit ude produces a larger change in output amplitude). when the drc1_knee2_op knee is enabled (?knee2? in fi gure 27), this introduces the vertical line
WM5102 production data w pd, may 2013, rev 4.0 74 in the response pattern illustrated, resulting in infini tely steep attenuation at this point in the response. the drc parameters are listed in table 13. ref parameter description 1 drc1_knee_ip input level at knee1 (db) 2 drc1_knee_op output level at knee2 (db) 3 drc1_hi_comp compression ratio above knee1 4 drc1_lo_comp compression ratio below knee1 5 drc1_knee2_ip input level at knee2 (db) 6 drc1_ng_exp expansion ratio below knee2 7 drc1_knee2_op output level at knee2 (db) table 13 drc response parameters the noise gate is enabled when the drc1_ng_ena r egister is set. when the noise gate is not enabled, parameters 5, 6, 7 above are ignored, and the drc1_lo_comp slope applies to all input signal levels below knee1. the drc1_knee2_op knee is enabled when the drc1_k nee2_op_ena register is set. when this bit is not set, then parameter 7 above is ignored, and the knee2 position always coincides with the low end of the drc1_lo_comp region. the ?knee1? point in figure 27 is determi ned by register fields drc1_knee_ip and drc1_knee_op. parameter y0, the output level for a 0db input, is not specified directly, but can be calculated from the other parameters, using the equation: y0 = drc1_knee_op - (drc1_knee_ip x drc1_hi_comp) gain limits the minimum and maximum gain applied by the drc is set by register fields drc1_mingain, drc1_maxgain and drc1_ng_mingain. these limit s can be used to alter the drc response from that illustrated in figure 27. if the range between maximum and minimum gain is reduced, then the extent of the dynamic range control is reduced. the minimum gain in the compression regions of the drc response is set by drc1_mingain. the mimimum gain in the noise gate region is se t by drc1_ng_mingain. the minimum gain limit prevents excessive attenuation of the signal path. the maximum gain limit set by drc1_maxgain pr events quiet signals (or silence) from being excessively amplified. dynamic characteristics the dynamic behaviour determines how quickly t he drc responds to changing signal levels. note that the drc responds to the average (rms) signal amplitude over a period of time. the drc1 _ atk determines how quickly the drc gain decr eases when the signal amplitude is high. the drc1 _ dcy determines how quickly the drc gain incr eases when the signal amplitude is low. these register fields are described in table 14. note that the register defaults are suitable for general purpose microphone use.
production data WM5102 w pd, may 2013, rev 4.0 75 anti-clip control the drc includes an anti-clip feature to avoid si gnal clipping when the input amplitude rises very quickly. this feature uses a feed- forward technique for early detection of a rising signal level. signal clipping is avoided by dynamically increasing the gain attack rate when required. the anti-clip feature is enabled using the drc1 _ anticlip bit. note that the feed-forward processing increas es the latency in the input signal path. note that the anti-clip feature operates entirely in the digital domain. it cannot be used to prevent signal clipping in the analogue domain nor in t he source signal. anal ogue clipping can only be prevented by reducing the analogue signal gai n or by adjusting the source signal. quick release control the drc includes a quick-release feature to handle s hort transient peaks that are not related to the intended source signal. for example, in handhel d microphone recording, transient signal peaks sometimes occur due to user handling, key pre sses or accidental tapping against the microphone. the quick release feature ensures that these transients do not cause the intended signal to be masked by the longer time constant of drc1 _ dcy. the quick-release feature is enabled by setting the drc1 _ qr bit. when this bit is enabled, the drc measures the crest factor (peak to rms ratio) of t he input signal. a high crest fa ctor is indicative of a transient peak that may not be related to the int ended source signal. if the crest factor exceeds the level set by drc1 _ qr_thr, then the normal decay rate (drc1_dcy) is ignored and a faster decay rate (drc1_qr_dcy) is used instead. signal activity detect the drc incorporates a configurabl e signal detect function, allowing the signal level at the drc input to be monitored and to be used to trigger other event s. this can be used to detect the presence of a microphone signal on an adc or digital mic channel , or can be used to detect an audio signal received over the digital audio interface. the drc signal detect function is enabled by setti ng drc1_sig_det register bit. (note that drc1 must also be enabled.) the detection th reshold is either a peak level (crest factor) or an rms level, depending on the drc1_sig_det_mode register bit. when peak level is selected, the threshold is determined by drc1_sig_det_pk, which defines the applicable crest factor (peak to rms ratio) threshold. if rms level is selected, then t he threshold is set using drc1_sig_det_rms. the drc signal detect function is an input to the in terrupt control circuit and can be used to trigger an interrupt event - see ?interrupts?. the drc signal detect signal can be output directly on a gpio pin as an external indication of the signal detection. see ?general purpose input / out put? to configure a gpio pin for this function. the control write sequencer can be triggered by the drc signal detect function. this is enabled using the drc1_wseq_sig_det_ena register bi t. see ?control write sequencer? for further details.
WM5102 production data w pd, may 2013, rev 4.0 76 gpio outputs from drc the dynamic range control (drc) ci rcuit provides a number of stat us outputs, which can be output directly on a gpio pin as an external indicati on of the drc status. see ?general purpose input / output? to configure a gpio pin for these functions. each of the drc status outputs is described below. the drc signal detect flag indicates that a signal is present on the respective signal path. the threshold level for signal detection is configurable using the register fields are described in table 14. the drc anti-clip flag indicates that the drc anti-c lip function has been triggered. in this event, the drc gain is decreasing in response to a rising signal level. the flag is asserted until the drc gain stablises. the drc decay flag indicates that the drc gain incr easing in response to a low level signal input. the flag is asserted until the drc gain stabilises. the drc noise gate flag indicates that the drc no ise gate function has been triggered, indicating that an idle condition has been detected in the signal path. the drc quick release flag indicates that the drc quick release functi on has been triggered. in this event, the drc gain is increasing rapidly followi ng detection of a short tr ansient peak. the flag is asserted until the drc gain stabilises. drc register controls the drc control registers are described in table 14. register address bit label default description r3585 (0e01h) fx_ctrl2 15:4 fx_sts [11:0] 000h lhpf, drc, eq enable status indicates the status of each of the respective signal processing functions. [11] = eq4 [10] = eq3 [9] = eq2 [8] = eq1 [7] = reserved [6] = reserved [5] = drc1 (right) [4] = drc1 (left) [3] = lhpf4 [2] = lhpf3 [1] = lhpf2 [0] = lhpf1 each bit is coded as: 0 = disabled 1 = enabled r3712 (0e80h) drc1 ctrl1 15:11 drc1_sig_det _rms [4:0] 00h drc1 signal detect rms threshold. this is the rms signal level for signal detect to be indicated when drc1_sig_det_mode=1. 00h = -30db 01h = -31.5db ?. (1.5db steps) 1eh = -75db 1fh = -76.5db
production data WM5102 w pd, may 2013, rev 4.0 77 register address bit label default description 10:9 drc1_sig_det _pk [1:0] 00 drc1 signal detect peak threshold. this is the peak/rms ratio, or crest factor, level for signal detect to be indicated when drc1_sig_det_mode=0. 00 = 12db 01 = 18db 10 = 24db 11 = 30db 8 drc1_ng_ena 0 drc1 noise gate enable 0 = disabled 1 = enabled 7 drc1_sig_det _mode 0 drc1 signal detect mode 0 = peak threshold mode 1 = rms threshold mode 6 drc1_sig_det 0 drc1 signal detect enable 0 = disabled 1 = enabled 5 drc1_knee2_ op_ena 0 drc1 knee2_op enable 0 = disabled 1 = enabled 4 drc1_qr 1 drc1 quick-release enable 0 = disabled 1 = enabled 3 drc1_anticli p 1 drc1 anti-clip enable 0 = disabled 1 = enabled 2 drc1_wseq_s ig_det_ena 0 drc1 signal detect write sequencer select 0 = disabled 1 = enabled r3713 (0e81h) drc1 ctrl2 12:9 drc1_atk [3:0] 0100 drc1 gain attack rate (seconds/6db) 0000 = reserved 0001 = 181us 0010 = 363us 0011 = 726us 0100 = 1.45ms 0101 = 2.9ms 0110 = 5.8ms 0111 = 11.6ms 1000 = 23.2ms 1001 = 46.4ms 1010 = 92.8ms 1011 = 185.6ms 1100 to 1111 = reserved
WM5102 production data w pd, may 2013, rev 4.0 78 register address bit label default description 8:5 drc1_dcy [3:0] 1001 drc1 gain decay rate (seconds/6db) 0000 = 1.45ms 0001 = 2.9ms 0010 = 5.8ms 0011 = 11.6ms 0100 = 23.25ms 0101 = 46.5ms 0110 = 93ms 0111 = 186ms 1000 = 372ms 1001 = 743ms 1010 = 1.49s 1011 = 2.97s 1100 to1111 = reserved 4:2 drc1_mingain [2:0] 100 drc1 minimum gain to attenuate audio signals 000 = 0db 001 = -12db (default) 010 = -18db 011 = -24db 100 = -36db 101 = reserved 11x = reserved 1:0 drc1_maxgai n [1:0] 11 drc1 maximum gain to boost audio signals (db) 00 = 12db 01 = 18db 10 = 24db 11 = 36db r3714 (0e82h) drc1 ctrl3 15:12 drc1_ng_min gain [3:0] 0000 drc1 minimum gain to attenuate audio signals when the noise gate is active. 0000 = -36db 0001 = -30db 0010 = -24db 0011 = -18db 0100 = -12db 0101 = -6db 0110 = 0db 0111 = 6db 1000 = 12db 1001 = 18db 1010 = 24db 1011 = 30db 1100 = 36db 1101 to 1111 = reserved 11:10 drc1_ng_exp [1:0] 00 drc1 noise gate slope 00 = 1 (no expansion) 01 = 2 10 = 4 11 = 8
production data WM5102 w pd, may 2013, rev 4.0 79 register address bit label default description 9:8 drc1_qr_thr [1:0] 00 drc1 quick-release threshold (crest factor in db) 00 = 12db 01 = 18db 10 = 24db 11 = 30db 7:6 drc1_qr_dcy [1:0] 00 drc1 quick-release decay rate (seconds/6db) 00 = 0.725ms 01 = 1.45ms 10 = 5.8ms 11 = reserved 5:3 drc1_hi_com p [2:0] 011 drc1 compressor slope (upper region) 000 = 1 (no compression) 001 = 1/2 010 = 1/4 011 = 1/8 100 = 1/16 101 = 0 110 = reserved 111 = reserved 2:0 drc1_lo_com p [2:0] 000 drc1 compressor slope (lower region) 000 = 1 (no compression) 001 = 1/2 010 = 1/4 011 = 1/8 100 = 0 101 = reserved 11x = reserved r3715 (0e83h) drc1 ctrl4 10:5 drc1_knee_ip [5:0] 000000 drc1 input signal level at the compressor ?knee?. 000000 = 0db 000001 = -0.75db 000010 = -1.5db ? (-0.75db steps) 111100 = -45db 111101 = reserved 11111x = reserved 4:0 drc1_knee_o p [4:0] 00000 drc1 output signal at the compressor ?knee?. 00000 = 0db 00001 = -0.75db 00010 = -1.5db ? (-0.75db steps) 11110 = -22.5db 11111 = reserved
WM5102 production data w pd, may 2013, rev 4.0 80 register address bit label default description r3716 (0e84h) drc1 ctrl5 9:5 drc1_knee2_i p [4:0] 00000 drc1 input signal level at the noise gate threshold ?knee2?. 00000 = -36db 00001 = -37.5db 00010 = -39db ? (-1.5db steps) 11110 = -81db 11111 = -82.5db only applicable when drc1_ng_ena = 1. 4:0 drc1_knee2_ op [4:0] 00000 drc1 output signal at the noise gate threshold ?knee2?. 00000 = -30db 00001 = -31.5db 00010 = -33db ? (-1.5db steps) 11110 = -75db 11111 = -76.5db only applicable when drc1_knee2_op_ena = 1. table 14 drc1 control registers the WM5102 performs automatic checks to confir m that the sysclk frequency is high enough to support the commanded drc and digital mixing func tions. if an attempt is made to enable a drc signal path, and there are insufficient sysclk cycles to support it, then the attempt will be unsuccessful. (note that any signal paths that ar e already active will not be affected under these circumstances.) the underclocked error can be moni tored using the gpio and/or in terrupt functions. see ?general purpose input / output? and ?interrupts? for further details. the fx_sts field in register r3585 indicates t he status of each of the eq, drc and lhpf signal paths. if an underclocked error condi tion occurs, then this register provides readback of which eq, drc or lhpf signal path(s) have been successfully enabled. the status bits in registers r1600 to r2920 indicate the status of each of the digital mixers. if an underclocked error condition occu rs, then these bits provide r eadback of which mixer(s) have been successfully enabled.
production data WM5102 w pd, may 2013, rev 4.0 81 low pass / high pass digital filter (lhpf) the digital core provides four low pass filter (lpf) / high pass filter (hpf) processing blocks as illustrated in figure 28. a 4-input mixer is asso ciated with each filter. the 4 input sources are selectable in each case, and independent volume cont rol is provided for each path. each low/high pass filter (lhpf) block supports 1 output. the low pass filter / high pass filter can be used to remove unwanted ?out of band? noise from a signal path. each filter can be configured eit her as a low pass filter or high pass filter. WM5102 supports 4 lhpf blocks, ie. n = 1, 2, 3 or 4 lhpfnmix_vol2 lhpfnmix_vol3 lhpfnmix_vol4 + lhpfnmix_vol1 lhpfnmix_src1 lhpfnmix_src3 lhpfnmix_src4 lhpfnmix_src2 lhpf1 (60h) lhpf2 (61h) lhpf3 (62h) lhpf4 (63h) lhpf low-pass filter (lpf) / high-pass filter (hpf) figure 28 digital core lpf/hpf blocks the lhpf1, lhpf2, lhpf3 and lhpf4 mixer control r egisters (see figure 28) are located at register addresses r2304 (900h) through to r2335 (91fh). the full list of digital mixer control registers is pr ovided in the ?register map? section (register r1600 through to r2920). generic register def initions are provided in table 7. the *_src n registers select the input source(s) for the respective lhpf processing blocks. note that the selected input source(s) must be configured for t he same sample rate as the lhpf to which they are connected. sample rate conver sion functions are available to s upport flexible interconnectivity - see ?asynchronous sample rate converter (as rc)? and ?isochronous sample rate converter (isrc)?. the bracketed numbers in figure 28, eg. ?(60h)? indicate the corresponding *_src n register setting for selection of that signal as an i nput to another digital core function. the sample rate for the lhpf function is configur ed using the fx_rate register - see table 20. note that the eq, drc and lhpf functions must all be configured for the same sample rate. sample rate conversion is required when routing the lhpf signal paths to any si gnal chain that is asynchronous and/or configured for a different sample rate. the control registers associated with the lhpf functions are described in table 15. the cut-off frequencies for the lhpf blocks are set using the coefficients held in registers r3777, r3781, r3785 and r3789 for lhpf1, lhpf2, lhpf3 and lhpf4 respectively. these coefficients are derived using tools provided in wolfson?s wisce? evaluation board control so ftware; please contact your local wolfson representative for more details.
WM5102 production data w pd, may 2013, rev 4.0 82 register address bit label default description r3585 (0e01h) fx_ctrl2 15:4 fx_sts [11:0] 000h lhpf, drc, eq enable status indicates the status of each of the respective signal pr ocessing functions. [11] = eq4 [10] = eq3 [9] = eq2 [8] = eq1 [7] = reserved [6] = reserved [5] = drc1 (right) [4] = drc1 (left) [3] = lhpf4 [2] = lhpf3 [1] = lhpf2 [0] = lhpf1 each bit is coded as: 0 = disabled 1 = enabled r3776 (0ec0h) hplpf1_ 1 1 lhpf1_mode 0 low/high pass filter 1 mode 0 = low-pass 1 = high-pass 0 lhpf1_ena 0 low/high pass filter 1 enable 0 = disabled 1 = enabled r3777 (0ec1h) hplpf1_ 2 15:0 lhpf1_coeff [15:0] 0000h low/high pass filter 1 frequency coefficient refer to wisce evaluation board control software for the deriviation of this field value. r3780 (0ec4h) hplpf2_ 1 1 lhpf2_mode 0 low/high pass filter 2 mode 0 = low-pass 1 = high-pass 0 lhpf2_ena 0 low/high pass filter 2 enable 0 = disabled 1 = enabled r3781 (0ec5h) hplpf2_ 2 15:0 lhpf2_coeff [15:0] 0000h low/high pass filter 2 frequency coefficient refer to wisce evaluation board control software for the deriviation of this field value. r3784 (0ec8h) hplpf3_ 1 1 lhpf3_mode 0 low/high pass filter 3 mode 0 = low-pass 1 = high-pass 0 lhpf3_ena 0 low/high pass filter 3 enable 0 = disabled 1 = enabled r3785 (0ec9h) hplpf3_ 2 15:0 lhpf3_coeff [15:0] 0000h low/high pass filter 3 frequency coefficient refer to wisce evaluation board control software for the deriviation of this field value. r3788 (0ecch) hplpf4_ 1 lhpf4_mode 0 low/high pass filter 4 mode 0 = low-pass 1 = high-pass
production data WM5102 w pd, may 2013, rev 4.0 83 register address bit label default description 1 0 lhpf4_ena 0 low/high pass filter 4 enable 0 = disabled 1 = enabled r3789 (0ecdh) hplpf4_ 2 15:0 lhpf4_coeff [15:0] 0000h low/high pass filter 4 frequency coefficient refer to wisce evaluation board control software for the deriviation of this field value. table 15 low pass filter / high pass filter control the WM5102 performs automatic checks to confir m that the sysclk frequency is high enough to support the commanded lhpf and digital mixing func tions. if an attempt is made to enable an lhpf signal path, and there are insufficient sysclk cycles to support it, then the attempt will be unsuccessful. (note that any signal paths that ar e already active will not be affected under these circumstances.) the underclocked error can be moni tored using the gpio and/or in terrupt functions. see ?general purpose input / output? and ?interrupts? for further details. the fx_sts field in register r3585 indicates t he status of each of the eq, drc and lhpf signal paths. if an underclocked error condi tion occurs, then this register provides readback of which eq, drc or lhpf signal path(s) have been successfully enabled. the status bits in registers r1600 to r2920 indicate the status of each of the digital mixers. if an underclocked error condition occu rs, then these bits provide r eadback of which mixer(s) have been successfully enabled.
WM5102 production data w pd, may 2013, rev 4.0 84 digital core dsp the digital core incorporates a programmable dsp block, as illustrated in figure 29. the dsp supports 8 inputs (left, right, aux1, aux2, ? aux6). a 4-input mixer is associated with the left and right inputs, providing further expansion of the number of input paths. each of the input sources is selectable, and independent volume control is prov ided for left and right input mixer channels. the dsp block supports 6 outputs. the functionality of the dsp is not fixed, and a wide range of audio enhancements algorithms may be performed. the procedure for configuring the WM5102 dsp functions is tailored to each customer?s application; please contact your local wo lfson representative for more details. for details of the dsp firmware requirements relating to clocking, register access, and code execution, refer to the ?dsp firmware control? section. figure 29 digital core dsp block the dsp1 mixer / input control registers (see fi gure 29) are located at register addresses r2368 (940h) through to r2383 (094fh). the full list of digital mixer control registers is pr ovided in the ?register map? section (register r1600 through to r2920). generic register def initions are provided in table 7. the *_src n registers select the input source(s) for t he dsp1 block. note that the selected input source(s) must be configured for the same sample rate as the dsp to which they are connected. sample rate conversion functi ons are available to support fl exible interconnectivity - see ?asynchronous sample rate converter (asrc)? and ?isochronous sample rate converter (isrc)?. the bracketed numbers in figure 29, eg. ?(68h)? indicate the corresponding *_src n register setting for selection of that signal as an i nput to another digital core function. the sample rate of the dsp input/output is confi gured using the respective dsp1_rate register - see table 20. sample rate conversion is required when routing the dsp1 signal paths to any signal chain that is asynchronous and/or configured for a different sample rate.
production data WM5102 w pd, may 2013, rev 4.0 85 the WM5102 performs automatic checks to confir m that the sysclk frequency is high enough to support the commanded dsp mixing functions. if an a ttempt is made to enable a dsp mixer path, and there are insufficient sysclk cycles to support i t, then the attempt will be unsuccessful. (note that any signal paths that are already active w ill not be affected under these circumstances.) the underclocked error condition c an be monitored using the gpio and/or interrupt functions. see ?general purpose input / output? and ?interrupts? for further details. the status bits in registers r1600 to r2920 indicate the status of each of the digital mixers. if an underclocked error condition occu rs, then these bits provide r eadback of which mixer(s) have been successfully enabled. the WM5102 supports two dsp status flags as outputs from the dsp. these are configurable within the dsp to provide external indication of the r equired function(s). the dsp status flags can be read using the dsp_irqn_sts registers descr ibed in table 86 (see ?interrupts?). the dsp status flags are inputs to the interrupt c ontrol circuit and can be used to trigger an interrupt event - see ?interrupts?. the dsp status flags can be output directly on a gpio pin as an external indication of the dsp status. see ?general purpose input / output? to configure a gpio pi n for this function. tone generator the WM5102 incorporates two 1khz tone generators which can be used for ? beep? functions through any of the audio signal paths. the phase relations hip between the two generators is configurable, providing flexibility in creating differ ential signals, or for test scenarios. figure 30 digital core tone generator the tone generators can be selected as input to any of the digital mixers or signal processing functions within the WM5102 digital core. the bracke ted numbers in figure 30, eg. ?(04h)? indicate the corresponding *_src n register setting for selection of that signal as an input to another digital core function. the sample rate for the tone generators is configur ed using the tone_rate register - see table 20. note that sample rate conversion is required w hen routing the tone generator output(s) to any signal chain that is asynchronous and/or conf igured for a different sample rate. the tone generators are enabled using the tone1_ena and tone2_ena register bits as described in table 16. the phase relationship is configured using tone_offset. the tone generators can also provi de a configurable dc signal level, for use as a test signal. the dc output is selected using the tonen_ovd register bits, and the dc signal amplitude is configured using the tonen_lvl registers, as described in table 16.
WM5102 production data w pd, may 2013, rev 4.0 86 register address bit label default description r32 (0020h) tone generator 1 9:8 tone_offset [1:0] 00 tone generator phase offset sets the phase of tone generator 2 relative to tone generator 1 00 = 0 degrees (in phase) 01 = 90 degrees ahead 10 = 180 degrees ahead 11 = 270 degrees ahead 5 tone2_ovd 0 tone generator 2 override 0 = disabled (1khz tone output) 1 = enabled (dc signal output) the dc signal level, when selected, is configured using tone2_lvl[23:0] 4 tone1_ovd 0 tone generator 1 override 0 = disabled (1khz tone output) 1 = enabled (dc signal output) the dc signal level, when selected, is configured using tone1_lvl[23:0] 1 tone2_ena 0 tone generator 2 enable 0 = disabled 1 = enabled 0 tone1_ena 0 tone generator 1 enable 0 = disabled 1 = enabled r33 (0021h) tone generator 2 15:0 tone1_lvl [23:8] 1000h tone generator 1 dc output level tone1_lvl [23:8] is coded as 2?s complement. bits [23:20] contain the integer portion; bits [19:0] contain the fractional portion. the digital core 0dbfs level corresponds to 1000_00h (+1) or f000_00h (-1). r34 (0022h) tone generator 3 7:0 tone1_lvl [7:0] 00h tone generator 1 dc output level tone1_lvl [23:8] is coded as 2?s complement. bits [23:20] contain the integer portion; bits [19:0] contain the fractional portion. the digital core 0dbfs level corresponds to 1000_00h (+1) or f000_00h (-1). r35 (0023h) tone generator 4 15:0 tone2_lvl [23:8] 1000h tone generator 2 dc output level tone2_lvl [23:8] is coded as 2?s complement. bits [23:20] contain the integer portion; bits [19:0] contain the fractional portion. the digital core 0dbfs level corresponds to 1000_00h (+1) or f000_00h (-1). r36 (0024h) tone generator 5 7:0 tone2_lvl [7:0] 00h tone generator 2 dc output level tone2_lvl [23:8] is coded as 2?s complement. bits [23:20] contain the integer portion; bits [19:0] contain the fractional portion. the digital core 0dbfs level corresponds to 1000_00h (+1) or f000_00h (-1). table 16 tone generator control
production data WM5102 w pd, may 2013, rev 4.0 87 noise generator the WM5102 incorporates a white noise generator, wh ich can be routed within the digital core. the main purpose of the noise generator is to provide ?com fort noise? in cases where silence (digital mute) is not desirable. figure 31 digital core noise generator the noise generator can be selected as input to any of the digital mixers or signal processing functions within the WM5102 digital core. the br acketed number (0dh) in figure 31 indicates the corresponding *_src n register setting for selection of the noise generator as an input to another digital core function. the sample rate for the noise generator is conf igured using the noise_ge n_rate register - see table 20. note that sample rate conversion is r equired when routing the noise generator output to any signal chain that is asynchronous and/or configured for a different sample rate. the noise generator is enabled using the noise_gen_ ena register bit as described in table 17. the signal level is confi gured using noise_gen_gain. register address bit label default description r112 (0070h) comfort noise generator 5 noise_gen_en a 0 noise generator enable 0 = disabled 1 = enabled 4:0 noise_gen_ga in [4:0] 00h noise generator signal level 00h = -114dbfs 01h = -108dbfs 02h = -102dbfs ?(6db steps) 11h = -6dbfs 12h = 0dbfs all other codes are reserved table 17 noise generator control haptic signal generator the WM5102 incorporates a signal generator for use with haptic devices (eg. mechanical vibration actuators). the haptic signal generator is compat ible with both eccentric rotating mass (erm) and linear resonant actuator (lra) haptic devices. the haptic signal generator is highly configurable, and includes the capability to execute a programmable event profile comprisi ng three distinct operating phases. the resonant frequency of the haptic signal output (for lra devices) is selectable, providing support for many different actuator components. the haptic signal generator is a digita l signal generator which is incorpor ated within the digital core of the WM5102. the haptic signal may be routed, via one of the digital core output mixers, to a class d speaker output for connection to the external haptic device, as illustrated in figure 32. (note that the digital pdm output paths may also be used for haptic signal output.)
WM5102 production data w pd, may 2013, rev 4.0 88 figure 32 digital core haptic signal generator the bracketed number (06h) in figur e 32 indicates the corresponding *_src n register setting for selection of the haptic signal generator as an input to another digital core function. the haptic signal generator is selected as input to one of the digital core output mixers by setting the *_src n register of the applicable output mixer to (06h). the sample rate for the haptic signal generator is configured using the h ap_rate register - see table 20. note that sample rate conversion is required when routing the haptic signal generator output to any signal chain that is asynchronous and/ or configured for a different sample rate. the haptic signal generator is configured for an erm or lra actuator using the hap_act register bit. the required resonant frequency is c onfigured using the lra_freq field. (note that the resonant frequency is only applicable to lra actuators.) the signal generator can be enabled in continuous m ode or configured for one-shot mode using the hap_ctrl register, as described in table 18. in o ne-shot mode, the output is triggered by writing to the oneshot_trig bit. in one-shot mode, the signal generator profile comp rises the distinct phases (1, 2, 3). the duration and intensity of each output phase is programmable. in continuous mode, the signal intensity is c ontrolled using the phase2_intensity field only. in the case of an erm actuator (hap_act = 0), the haptic output is a dc signal level, which may be positive or negative, as selected by the *_intensity registers. for an lra actuator (hap_act = 1), the haptic out put is an ac signal; selecting a negative signal level corresponds to a 180 degree phase inversion. in some applications, phase inversion may be desirable during the final phase, to halt t he physical motion of the haptic device. register address bit label default description r144 (0090h) haptics control 1 4 oneshot_trig 0 haptic one-shot trigger writing ?1? starts the one-shot profile (ie. phase 1, phase 2, phase 3) 3:2 hap_ctrl [1:0] 00 haptic signal generator control 00 = disabled 01 = continuous 10 = one-shot 11 = reserved 1 hap_act 0 haptic actuator select 0 = eccentric rotating mass (erm) 1 = linear resonant actuator (lra)
production data WM5102 w pd, may 2013, rev 4.0 89 register address bit label default description r145 (0091h) haptics control 2 14:0 lra_freq [14:0] 7fffh haptic resonant frequency selects the haptic signal frequency (lra actuator only, hap_act = 1) haptic frequency (hz) = system clock / (2 x (lra_freq+1)) where system clock = 6.144mhz or 5.6448mhz, derived by division from sysclk or asyncclk. if hap_rate<1000, then sysclk is the clock source, and the applicable system clock frequency is determined by sysclk. if hap_rate>=1000, then asyncclk is the clock source, and the applicable system clock frequency is determined by asyncclk. valid for haptic frequency in the range 100hz to 250hz for 6.144mhz system clock: 77ffh = 100hz 4491h = 175hz 2fffh = 250hz for 5.6448mhz system clock: 6e3fh = 100hz 3effh = 175hz 2c18h = 250hz r146 (0092h) haptics phase 1 intensity 7:0 phase1_inten sity [7:0] 00h haptic output level (phase 1) selects the signal intensity of phase 1 in one-shot mode. coded as 2?s complement. range is +/- full scale (fs). for erm actuator, this selects the dc signal level for the haptic output. for lra actuator, this selects the ac peak amplitude; negative values correspond to a 180 degree phase shift. r147 (0093h) haptics control phase 1 duration 8:0 phase1_durat ion [8:0] 000h haptic output duration (phase 1) selects the duration of phase 1 in one- shot mode. 000h = 0ms 001h = 0.625ms 002h = 1.25ms ? (0.625ms steps) 1ffh = 319.375ms
WM5102 production data w pd, may 2013, rev 4.0 90 register address bit label default description r148 (0094h) haptics phase 2 intensity 7:0 phase2_inten sity [7:0] 00h haptic output level (phase 2) selects the signal intensity in continuous mode or phase 2 of one-shot mode. coded as 2?s complement. range is +/- full scale (fs). for erm actuator, this selects the dc signal level for the haptic output. for lra actuator, this selects the ac peak amplitude; negative values correspond to a 180 degree phase shift. r149 (0095h) haptics phase 2 duration 10:0 phase2_durat ion [10:0] 000h haptic output duration (phase 2) selects the duration of phase 2 in one- shot mode. 000h = 0ms 001h = 0.625ms 002h = 1.25ms ? (0.625ms steps) 7ffh = 1279.375ms r150 (0096h) haptics phase 3 intensity 7:0 phase3_inten sity [7:0] 00h haptic output level (phase 3) selects the signal intensity of phase 3 in one-shot mode. coded as 2?s complement. range is +/- full scale (fs). for erm actuator, this selects the dc signal level for the haptic output. for lra actuator, this selects the ac peak amplitude; negative values correspond to a 180 degree phase shift. r151 (0097h) haptics phase 3 duration 8:0 phase3_durat ion [8:0] 000h haptic output duration (phase 3) selects the duration of phase 3 in one- shot mode. 000h = 0ms 001h = 0.625ms 002h = 1.25ms ? (0.625ms steps) 1ffh = 319.375ms r152 (0098h) haptics status 0 oneshot_sts 0 haptic one-shot status 0 = one-shot event not in progress 1 = one-shot event in progress table 18 haptic signal generator control
production data WM5102 w pd, may 2013, rev 4.0 91 pwm generator the WM5102 incorporates two pulse width modulat ion (pwm) signal generators as illustrated in figure 33. the duty cycle of each pwm signal can be modulated by an audio source, or can be set to a fixed value using a control register setting. a 4-input mixer is associated with each pwm generat or. the 4 input sources are selectable in each case, and independent volume control is provided for each path. the pwm signal generators can be output directly on a gpio pin. see ?general purpose input / output? to configure a gpio pin for this function. note that the pwm signal generators cannot be select ed as input to the digital mixers or signal processing functions within the WM5102 digital core. figure 33 digital core pulse width modulation (pwm) generator the pwm1 and pwm2 mixer control registers (see figure 33) are located at register addresses r1600 (640h) through to r1615 (64fh). the full list of digital mixer control registers is pr ovided in the ?register map? section (register r1600 through to r2920). generic register def initions are provided in table 7. the *_src n registers select the input source(s) for the re spective mixers. note that the selected input source(s) must be configured for the same sample rate as the mixer to which they are connected. sample rate conversion functi ons are available to support fl exible interconnectivity - see ?asynchronous sample rate converter (asrc)? and ?isochronous sample rate converter (isrc)?.
WM5102 production data w pd, may 2013, rev 4.0 92 the pwm sample rate (cycle time) is configured us ing the pwm_rate register - see table 20. note that sample rate conversion is required when linki ng the pwm generators to any signal chain that is asynchronous and/or configured for a different sample rate. the pwm generators are enabled using pwm1_ena and pwm2_ena respectively, as described in table 19. under default conditions (pwm n _ovd = 0), the duty cycle of the pwm generators is controlled by an audio signal path; a 4-input mixer is associated wi th each pwm generator, as illustrated in figure 33. when the pwm n _ovd bit is set, the duty cycle of the re spective pwm generator is set to a fixed ratio; in this case, the duty cycle ratio is configur able using the pwm n _lvl registers. the pwm generator clock frequency is selected us ing pwm_clk_sel. for best performance, this register should be set to the highes t available setting. note that the pwm generator clock must not be set to a higher frequency than sysclk (if pwm_rate<1000) or asyncclk (if pwm_rate 1000). register address bit label default description r48 (0030h) pwm drive 1 10:8 pwm_clk_sel [2:0] 000 pwm clock select 000 = 6.144mhz (5.6448mhz) 001 = 12.288mhz (11.2896mhz) 010 = 24.576mhz (22.5792mhz) all other codes are reserved the frequencies in brackets apply for 44.1khz-related sample rates only. pwm_clk_sel controls the resolution of the pwm generator; higher settings correspond to higher resolution. the pwm clock must be less than or equal to sysclk (if pwm_rate<1000) or less than or equal to asyncclk (if pwm_rate>=1000). 5 pwm2_ovd 0 pwm2 generator override 0 = disabled (pwm duty cycle is controlled by audio source) 1 = enabled (pwm duty cycle is controlled by pwm2_lvl). 4 pwm1_ovd 0 pwm1 generator override 0 = disabled (pwm1 duty cycle is controlled by audio source) 1 = enabled (pwm1 duty cycle is controlled by pwm1_lvl). 1 pwm2_ena 0 pwm2 generator enable 0 = disabled 1 = enabled 0 pwm1_ena 0 pwm1 generator enable 0 = disabled 1 = enabled r49 (0031h) pwm drive 2 9:0 pwm1_lvl [9:0] 100h pwm1 override level sets the pwm1 duty cycle when pwm1_ovd=1. coded as 2?s complement. 000h = 50% duty cycle 100h = 0% duty cycle r50 (0032h) pwm drive 3 9:0 pwm2_lvl [9:0] 100h pwm2 override level sets the pwm2 duty cycle when pwm2_ovd=1. coded as 2?s complement. 000h = 50% duty cycle 100h = 0% duty cycle table 19 pulse width modulation (pwm) generator control
production data WM5102 w pd, may 2013, rev 4.0 93 the WM5102 performs automatic checks to confir m that the sysclk frequency is high enough to support the digital mixer paths. if an attempt is made to enable a pwm signal mixer path, and there are insufficient sysclk cycles to support it, t hen the attempt will be unsuccessful. (note that any signal paths that are already active will not be affected under these circumstances.) the underclocked error condition c an be monitored using the gpio and/or interrupt functions. see ?general purpose input / output? and ?interrupts? for further details. the status bits in registers r1600 to r2920 indicate the status of each of the digital mixers. if an underclocked error condition occu rs, then these bits provide r eadback of which mixer(s) have been successfully enabled. sample rate control the WM5102 supports multiple signal paths through t he digital core. stereo full-duplex sample rate conversion is provided to allow digital audio to be routed between in terfaces operating at different sample rates and/or referenced to asynchronous clock domains. two independent clock domains are supported, refe renced to sysclk and asyncclk respectively, as described in ?clocking and sample rates?. every di gital signal path must be synchronised either to sysclk or to asyncclk. up to five different sample rates may be in use at any time on the WM5102. three of these sample rates must be synchronised to sysclk; the remaini ng two, where required, must be synchronised to asyncclk. sample rate conversion is required when routing any audio path between digital functions that are asynchronous and/or configured for different sample rates. the asynchronous sample rate converter (asrc) provides two stereo signal paths between the sysclk and asyncclk domains. the asrc is described later, and is illustrated in figure 36. there are two isochronous sample rate converters (isrcs). these provi de two signal paths each between sample rates on the sysclk domain, or between sample rates on the asyncclk domain. the isrcs are described later, and are illustrated in figure 37. the sample rate of different blocks within the WM5102 digital core are controlled as illustrated in figure 34 and figure 35 - the *_rate registers select the applicable sample rate for each respective group of digital functions.
WM5102 production data w pd, may 2013, rev 4.0 94 figure 34 digital core sample rate control (internal signal processing)
production data WM5102 w pd, may 2013, rev 4.0 95 figure 35 digital core sample rate control (external digital interfaces) the input signal paths may be selected as input to t he digital mixers or signal processing functions. the sample rate for the input signal paths is configured using the in_rate register. the output signal paths are derived from the respecti ve output mixers. the sample rate for the output signal paths is configured using the out_rate register. the sample rate of the aec loopback path is also set by the out_rate register. the aifn rx inputs may be selected as input to the digital mixers or signal processing functions. the aifn tx outputs are derived from the respective output mixers. the sample rates for digital audio interfaces (aif1, aif2 and aif3) are configur ed using the aif1_rate, aif2_rate and aif3_rate registers respectively. the slimbus interface supports up to 8 input c hannels and 8 output channels. the sample rate of each channel can be configured independently, us ing the slimtxn_rate and slimrxn_rate registers. note that the slimbus interface provides simultaneous support for sysclk-referenced and asyncclk-referenced sample rates on different channels. for exampl e, 48khz and 44.1khz slimbus audio paths can be simultaneously supported.
WM5102 production data w pd, may 2013, rev 4.0 96 the eq, lhpf and drc functions can be enabled in any signal path within the digital core. the sample rate for these functions is configured using the fx_rate r egister. note that the eq, drc and lhpf functions must all be configured for the same sample rate. the dsp functions can be enabled in any signal path within the digital core. the applicable sample rates are configured using the dsp1_rate register. the tone generators and noise generator can be selected as input to any of the digital mixers or signal processing functions. the sample rates for thes e sources are configured using the tone_rate and noise_gen_rate registers respectively. the haptic signal generator can be used to control an external vibe actuator, which can be driven directly by the class d speaker output. the sample rate for the haptic signal generator is configured using the hap_rate register. the pwm signal generators can be modulated by an audi o source, derived from the associated signal mixers. the sample rate (cycle time) for t he pwm signal generators is configured using the pwm_rate register. the sample rate control register s are described in table 20. refer to the register descriptions for details of the valid selections in each case. note that the input (adc) and output (dac) signal paths must always be associated with the sysclk cl ocking domain and are therefore synchronous to each other. the control registers associated with the as rc and isrcs are described in table 21 and table 22 respectively within the following sections. register address bit label default description r32 (0020h) tone generator 1 14:11 tone_rate [3:0] 0000 tone generator sample rate 0000 = sample_rate_1 0001 = sample_rate_2 0010 = sample_rate_3 1000 = async_sample_rate_1 1001 = async_sample_rate_2 all other codes are reserved. the selected sample rate is valid in the range 8khz to 192khz. r48 (0030h) pwm drive 1 14:11 pwm_rate [3:0] 0000 pwm frequency (sample rate) 0000 = sample_rate_1 0001 = sample_rate_2 0010 = sample_rate_3 1000 = async_sample_rate_1 1001 = async_sample_rate_2 all other codes are reserved. the selected sample rate is valid in the range 4khz to 192khz. r112 0070h) comfort noise generator 14:11 noise_gen_ra te [3:0] 0000 noise generator sample rate 0000 = sample_rate_1 0001 = sample_rate_2 0010 = sample_rate_3 1000 = async_sample_rate_1 1001 = async_sample_rate_2 all other codes are reserved. the selected sample rate is valid in the range 4khz to 192khz.
production data WM5102 w pd, may 2013, rev 4.0 97 register address bit label default description r144 0090h) haptics control 1 14:11 hap_rate [3:0] 0000 haptic signal generator sample rate 0000 = sample_rate_1 0001 = sample_rate_2 0010 = sample_rate_3 1000 = async_sample_rate_1 1001 = async_sample_rate_2 all other codes are reserved. the selected sample rate is valid in the range 8khz to 192khz. r707 (02c3h) mic noise mix control 1 14:11 micmute_rate [3:0] 0000 mic mute mixer sample rate 0000 = sample_rate_1 0001 = sample_rate_2 0010 = sample_rate_3 1000 = async_sample_rate_1 1001 = async_sample_rate_2 all other codes are reserved. the selected sample rate is valid in the range 8khz to 192khz. r776 (0308h) input rate 14:11 in_rate [3:0] 0000 input signal paths sample rate 0000 = sample_rate_1 0001 = sample_rate_2 0010 = sample_rate_3 all other codes are reserved. the selected sample rate is valid in the range 8khz to 192khz. r1032 (0408h) output rate 1 14:11 out_rate [3:0] 0000 output signal paths sample rate 0000 = sample_rate_1 0001 = sample_rate_2 0010 = sample_rate_3 all other codes are reserved. the selected sample rate is valid in the range 8khz to 96khz. r1283 (0503h) aif1 rate ctrl 3:0 aif1_rate [3:0] 0000 aif1 audio interface sample rate 0000 = sample_rate_1 0001 = sample_rate_2 0010 = sample_rate_3 1000 = async_sample_rate_1 1001 = async_sample_rate_2 all other codes are reserved. the selected sample rate is valid in the range 4khz to 192khz. r1347 (0543h) aif2 rate ctrl 3:0 aif2_rate [3:0] 0000 aif2 audio interface sample rate 0000 = sample_rate_1 0001 = sample_rate_2 0010 = sample_rate_3 1000 = async_sample_rate_1 1001 = async_sample_rate_2 all other codes are reserved. the selected sample rate is valid in the range 4khz to 192khz.
WM5102 production data w pd, may 2013, rev 4.0 98 register address bit label default description r1411 (0583h) aif3 rate ctrl 3:0 aif3_rate [3:0] 0000 aif3 audio interface sample rate 0000 = sample_rate_1 0001 = sample_rate_2 0010 = sample_rate_3 1000 = async_sample_rate_1 1001 = async_sample_rate_2 all other codes are reserved. the selected sample rate is valid in the range 4khz to 192khz. r1509 (05e5h) slimbus rates 1 14:11 slimrx2_rate [3:0] 0000 slimbus rx channel 2 sample rate 0000 = sample_rate_1 0001 = sample_rate_2 0010 = sample_rate_3 1000 = async_sample_rate_1 1001 = async_sample_rate_2 all other codes are reserved. the selected sample rate is valid in the range 4khz to 192khz. 6:3 slimrx1_rate [3:0] 0000 slimbus rx channel 1 sample rate 0000 = sample_rate_1 0001 = sample_rate_2 0010 = sample_rate_3 1000 = async_sample_rate_1 1001 = async_sample_rate_2 all other codes are reserved. the selected sample rate is valid in the range 4khz to 192khz. r1510 (05e6h) slimbus rates 2 14:11 slimrx4_rate [3:0] 0000 slimbus rx channel 4 sample rate 0000 = sample_rate_1 0001 = sample_rate_2 0010 = sample_rate_3 1000 = async_sample_rate_1 1001 = async_sample_rate_2 all other codes are reserved. the selected sample rate is valid in the range 4khz to 192khz. 6:3 slimrx3_rate [3:0] 0000 slimbus rx channel 3 sample rate 0000 = sample_rate_1 0001 = sample_rate_2 0010 = sample_rate_3 1000 = async_sample_rate_1 1001 = async_sample_rate_2 all other codes are reserved. the selected sample rate is valid in the range 4khz to 192khz. r1511 (05e7h) slimbus rates 3 14:11 slimrx6_rate [3:0] 0000 slimbus rx channel 6 sample rate 0000 = sample_rate_1 0001 = sample_rate_2 0010 = sample_rate_3 1000 = async_sample_rate_1 1001 = async_sample_rate_2 all other codes are reserved. the selected sample rate is valid in the range 4khz to 192khz.
production data WM5102 w pd, may 2013, rev 4.0 99 register address bit label default description 6:3 slimrx5_rate [3:0] 0000 slimbus rx channel 5 sample rate 0000 = sample_rate_1 0001 = sample_rate_2 0010 = sample_rate_3 1000 = async_sample_rate_1 1001 = async_sample_rate_2 all other codes are reserved. the selected sample rate is valid in the range 4khz to 192khz. r1512 (05e8h) slimbus rates 4 14:11 slimrx8_rate [3:0] 0000 slimbus rx channel 8 sample rate 0000 = sample_rate_1 0001 = sample_rate_2 0010 = sample_rate_3 1000 = async_sample_rate_1 1001 = async_sample_rate_2 all other codes are reserved. the selected sample rate is valid in the range 4khz to 192khz. 6:3 slimrx7_rate [3:0] 0000 slimbus rx channel 7 sample rate 0000 = sample_rate_1 0001 = sample_rate_2 0010 = sample_rate_3 1000 = async_sample_rate_1 1001 = async_sample_rate_2 all other codes are reserved. the selected sample rate is valid in the range 4khz to 192khz. r1513 (05e9h) slimbus rates 5 14:11 slimtx2_rate [3:0] 0000 slimbus tx channel 2 sample rate 0000 = sample_rate_1 0001 = sample_rate_2 0010 = sample_rate_3 1000 = async_sample_rate_1 1001 = async_sample_rate_2 all other codes are reserved. the selected sample rate is valid in the range 4khz to 192khz. 6:3 slimtx1_rate [3:0] 0000 slimbus tx channel 1 sample rate 0000 = sample_rate_1 0001 = sample_rate_2 0010 = sample_rate_3 1000 = async_sample_rate_1 1001 = async_sample_rate_2 all other codes are reserved. the selected sample rate is valid in the range 4khz to 192khz. r1514 (05eah) slimbus rates 6 14:11 slimtx4_rate [3:0] 0000 slimbus tx channel 4 sample rate 0000 = sample_rate_1 0001 = sample_rate_2 0010 = sample_rate_3 1000 = async_sample_rate_1 1001 = async_sample_rate_2 all other codes are reserved. the selected sample rate is valid in the range 4khz to 192khz.
WM5102 production data w pd, may 2013, rev 4.0 100 register address bit label default description 6:3 slimtx3_rate [3:0] 0000 slimbus tx channel 3 sample rate 0000 = sample_rate_1 0001 = sample_rate_2 0010 = sample_rate_3 1000 = async_sample_rate_1 1001 = async_sample_rate_2 all other codes are reserved. the selected sample rate is valid in the range 4khz to 192khz. r1515 (05ebh) slimbus rates 7 14:11 slimtx6_rate [3:0] 0000 slimbus tx channel 6 sample rate 0000 = sample_rate_1 0001 = sample_rate_2 0010 = sample_rate_3 1000 = async_sample_rate_1 1001 = async_sample_rate_2 all other codes are reserved. the selected sample rate is valid in the range 4khz to 192khz. 6:3 slimtx5_rate [3:0] 0000 slimbus tx channel 5 sample rate 0000 = sample_rate_1 0001 = sample_rate_2 0010 = sample_rate_3 1000 = async_sample_rate_1 1001 = async_sample_rate_2 all other codes are reserved. the selected sample rate is valid in the range 4khz to 192khz. r1516 (05ech) slimbus rates 8 14:11 slimtx8_rate [3:0] 0000 slimbus tx channel 8 sample rate 0000 = sample_rate_1 0001 = sample_rate_2 0010 = sample_rate_3 1000 = async_sample_rate_1 1001 = async_sample_rate_2 all other codes are reserved. the selected sample rate is valid in the range 4khz to 192khz. 6:3 slimtx7_rate [3:0] 0000 slimbus tx channel 7 sample rate 0000 = sample_rate_1 0001 = sample_rate_2 0010 = sample_rate_3 1000 = async_sample_rate_1 1001 = async_sample_rate_2 all other codes are reserved. the selected sample rate is valid in the range 4khz to 192khz. r3584 (0e00h) fx_ctrl 15:12 fx_rate [3:0] 0000 fx sample rate (eq, lhpf, drc) 0000 = sample_rate_1 0001 = sample_rate_2 0010 = sample_rate_3 1000 = async_sample_rate_1 1001 = async_sample_rate_2 all other codes are reserved. the selected sample rate is valid in the range 8khz to 192khz.
production data WM5102 w pd, may 2013, rev 4.0 101 register address bit label default description r4352 (1100h) dsp1 control 1 15:12 dsp1_rate [3:0] 0000 dsp1 sample rate 0000 = sample_rate_1 0001 = sample_rate_2 0010 = sample_rate_3 1000 = async_sample_rate_1 1001 = async_sample_rate_2 all other codes are reserved. the selected sample rate is valid in the range 4khz to 192khz. table 20 digital core sample rate control asynchronous sample rate converter (asrc) the WM5102 supports multiple signal paths through the digital core. two independent clock domains are supported, referenced to sysclk and asynccl k respectively, as described in ?clocking and sample rates?. every digital signal path must be synchronised either to sysclk or to asyncclk. the asynchronous sample rate converter (asrc) provides two stereo signal paths between the sysclk and asyncclk domains, as illustrated in figure 36. the sample rate on the sysclk domain is select ed using the asrc_rate1 register - the rate can be set equal to sample_rate_1, sample_rate_2 or sample_rate_3. the sample rate on the asyncclk domain is selected using the asrc_rate2 register - the rate can be set equal to async_sample_rate_1 or async_sample_rate_2. see ?clocking and sample rates? for details of the sample rate control registers. the asrc supports sample rates in the range 8k hz to 48khz only. the applicable sample_rate_n and async_sample_rate_n registers must each se lect sample rates between 8khz and 48khz when any asrc path is enabled. the asrc1 left and asrc1 right paths conver t from the sysclk domain to the asyncclk domain. these paths are enabled using the asrc1l_ena and asrc1r_ena register bits respectively. the asrc2 left and asrc2 right paths conver t from the asyncclk domain to the sysclk domain. these paths are enabled using the asrc2l_ena and asrc2r_ena register bits respectively. synchronisation (lock) between different clock dom ains is not instantaneous when the clocking or sample rate configurations are updated. the lock stat us of each asrc path is an input to the interrupt control circuit and can be used to trigger an interrupt event - see ?interrupts?. the asrc lock status of each asrc path can be out put directly on a gpio pin as an external indication of asrc lock. see ?general purpose input / output? to configure a gpio pin for this function. the WM5102 performs automatic checks to confir m that the sysclk or asyncclk frequency is high enough to support the commanded asrc and digital mi xing functions. if an attempt is made to enable an asrc signal path, and there are insufficient sysclk or asynclk cycles to support it, then the attempt will be unsuccessful. (note that any signal paths that are already active will not be affected under these circumstances.) the underclocked error can be moni tored using the gpio and/or in terrupt functions. see ?general purpose input / output? and ?interrupts? for further details. the status bits in register r3809 indicate t he status of each of the asrc signal paths. if an underclocked error condition occurs , then these bits provide readba ck of which asrc signal path(s) have been successfully enabled.
WM5102 production data w pd, may 2013, rev 4.0 102 the status bits in registers r1600 to r2920 indicate the status of each of the digital mixers. if an underclocked error condition occu rs, then these bits provide r eadback of which mixer(s) have been successfully enabled. the asynchronous sample rate converter (asrc) si gnal paths and control registers are illustrated in figure 36. asrc1r_ena asrc1l_ena asrc1l_src asrc1r_src asrc1 left (90h) asrc1 right (91h) asrc2r_ena asrc2l_ena asrc2l_src asrc2r_src asrc2 left (92h) asrc2 right (93h) asrc_rate1 (= sample_rate_n) asrc_rate2 (= async_sample_rate_n) the asrc provides asynchronous conversion between the sysclk and asyncclk clock domains. asrc_rate1 identifies the sysclk-related sample rate (sample_rate_n). asrc_rate2 identifies the asyncclk-related sample rate (async_sample_rate_n). figure 36 asynchronous sample rate converters (asrcs) the asrc1 and asrc2 input control registers (see figure 36) are located at register addresses r2688 (a80h) through to r2712 (a98h). the full list of digital mixer control registers is pr ovided in the ?register map? section (register r1600 through to r2920). generic register def initions are provided in table 7. the *_src n registers select the input source(s) for the respective asrc processing blocks. note that the selected input source(s) must be configured for t he same sample rate as the asrc to which they are connected. the bracketed numbers in figure 36, eg. ?(90h)? indicate the corresponding *_src n register setting for selection of that signal as an i nput to another digital core function. the register bits associated with the asrcs are described in table 21.
production data WM5102 w pd, may 2013, rev 4.0 103 register address bit label default description r3808 (0ee0h) asrc_en able 3 asrc2l_ena 0 asrc2 left enable (left asrc channel from asyncclk domain to sysclk domain) 0 = disabled 1 = enabled 2 asrc2r_ena 0 asrc2 right enable (right asrc channel from asyncclk domain to sysclk domain) 0 = disabled 1 = enabled 1 asrc1l_ena 0 asrc1 left enable (left asrc channel from asyncclk domain to sysclk domain) 0 = disabled 1 = enabled 0 asrc1r_ena 0 asrc1 right enable (right asrc channel from asyncclk domain to sysclk domain) 0 = disabled 1 = enabled r3809 (0ee1h) asrc_st atus 3 asrc2l_ena_s ts 0 asrc2 left enable status (left asrc channel from asyncclk domain to sysclk domain) 0 = disabled 1 = enabled 2 asrc2r_ena_s ts 0 asrc2 right enable status (right asrc channel from asyncclk domain to sysclk domain) 0 = disabled 1 = enabled 1 asrc1l_ena_s ts 0 asrc1 left enable status (left asrc channel from asyncclk domain to sysclk domain) 0 = disabled 1 = enabled 0 asrc1r_ena_s ts 0 asrc1 right enable status (right asrc channel from asyncclk domain to sysclk domain) 0 = disabled 1 = enabled r3810 (0ee2h) asrc_ra te1 15:12 asrc_rate1 [3:0] 0000 asrc sample rate select for sysclk domain 0000 = sample_rate_1 0001 = sample_rate_2 0010 = sample_rate_3 all other codes are reserved. the selected sample rate is valid in the range 8khz to 48khz. r3811 (0ee3h) asrc_ra te2 15:12 asrc_rate2 [3:0] 1000 asrc sample rate select for asyncclk domain 1000 = async_sample_rate_1 1001 = async_sample_rate_2 all other codes are reserved. the selected sample rate is valid in the range 8khz to 48khz. table 21 digital core asrc control
WM5102 production data w pd, may 2013, rev 4.0 104 isochronous sample rate converter (isrc) the WM5102 supports multiple signal paths through t he digital core. the isochronous sample rate converters (isrcs) provide sa mple rate conversion between synchronised sample rates on the sysclk clock domain, or between synchronised sample rates on the asyncclk clock domain. there are two isochronous sample rate converters (i srcs). each of these pr ovides two signal paths between two different sample rates, as illustrated in figure 37. the sample rates associated with each isrc can be set independently. note that the two sample rates associated with any single isrc must both be referenced to the same clock domain (sysclk or asyncclk). when an isrc is used on the sysclk domain, then the associated sample rates may be selected from sample_rate_1, sample_rate_2 or sample_rate_3. when an isrc is used on the asyncclk domain, then the associated sample rates are async_sample_rate_1 and async_sample_rate_2. see ?clocking and sample rates? for details of the sample rate control registers. each isrc supports sample rates in the range 8k hz to 192khz. the higher of the sample rates associated with each isrc must be an integer multiple of the lower sample rate; integer ratios in the range 1 to 6 are supported. each isrc converts between a sample rate selected by isrcn_fsl and a sample rate selected by isrcn_fsh, (where ?n? identifies the applicable isrc 1 or 2). note that, in each case, the higher of the two sample rates must be selected by isrcn_fsh. the isrcn ?interpolation? paths (increasing sample rate) ar e enabled using the isrcn_int1_ena and isrcn_int2_ena register bits. the isrcn ?decimation? paths (decreasing sample rate) are enabled using the isrcn_dec1_ena and isrcn_dec2_ena register bits. a notch filter is provided in each of the is rc paths; these are enabled using the isrcn_notch_ena bits. the filter is configured automatically a ccording to the applicable sample rate(s). it is recommended to enable the filter for typical applicati ons. disabling the filter will provide maximum ?pass? bandwidth, at the expense of degraded stopband attenuation. the WM5102 performs automatic checks to confir m that the sysclk frequency is high enough to support the commanded isrc and digital mixing func tions. if an attempt is made to enable an isrc signal path, and there are insufficient sysclk cycles to support it, then the attempt will be unsuccessful. (note that any signal paths that ar e already active will not be affected under these circumstances.) the underclocked error condition c an be monitored using the gpio and/or interrupt functions. see ?general purpose input / output? and ?interrupts? for further details. the status bits in registers r1600 to r2920 indicate the status of each of the digital mixers. if an underclocked error condition occu rs, then these bits provide r eadback of which mixer(s) have been successfully enabled. the isochronous sample rate converter (isrc) si gnal paths and control registers are illustrated in figure 37.
production data WM5102 w pd, may 2013, rev 4.0 105 figure 37 isochronous sample rate converters (isrcs) the isrc input control registers (see figure 37) are located at register addresses r2816 (b00h) through to r2920 (0b68h). the full list of digital mixer control registers is pr ovided in the ?register map? section (register r1600 through to r2920). generic register def initions are provided in table 7. the *_src registers select the input source(s) for the respective isrc processing blocks. note that the selected input source(s) must be configured for t he same sample rate as the isrc to which they are connected. the bracketed numbers in figure 37, eg. ?(a4h)? indi cate the corresponding *_src register setting for selection of that signal as an input to another digital core function. the register bits associated with the isrcs are described in table 22.
WM5102 production data w pd, may 2013, rev 4.0 106 register address bit label default description r3824 (0ef0h) isrc 1 ctrl 1 14:11 isrc1_fsh [3:0] 0000 isrc1 high sample rate (sets the higher of the isrc1 sample rates) 0000 = sample_rate_1 0001 = sample_rate_2 0010 = sample_rate_3 1000 = async_sample_rate_1 1001 = async_sample_rate_2 all other codes are reserved. the selected sample rate is valid in the range 8khz to 192khz. the isrc1_fsh and isrc1_fsl fields must both select sample rates referenced to the same clock domain (sysclk or asyncclk). r3825 (0ef1h) isrc 1 ctrl 2 14:11 isrc1_fsl [3:0] 0000 isrc1 low sample rate (sets the lower of the isrc1 sample rates) 0000 = sample_rate_1 0001 = sample_rate_2 0010 = sample_rate_3 1000 = async_sample_rate_1 1001 = async_sample_rate_2 all other codes are reserved. the selected sample rate is valid in the range 8khz to 192khz. the isrc1_fsh and isrc1_fsl fields must both select sample rates referenced to the same clock domain (sysclk or asyncclk). r3826 (0ef2h) isrc 1 ctrl 3 15 isrc1_int1_en a 0 isrc1 int1 enable (interpolation channel 1 path from isrc1_fsl rate to isrc1_fsh rate) 0 = disabled 1 = enabled 14 isrc1_int2_en a 0 isrc1 int2 enable (interpolation channel 2 path from isrc1_fsl rate to isrc1_fsh rate) 0 = disabled 1 = enabled 9 isrc1_dec1_en a 0 isrc1 dec1 enable (decimation channel 1 path from isrc1_fsh rate to isrc1_fsl rate) 0 = disabled 1 = enabled 8 isrc1_dec2_en a 0 isrc1 dec2 enable (decimation channel 2 path from isrc1_fsh rate to isrc1_fsl rate) 0 = disabled 1 = enabled 0 isrc1_notch_ ena 0 isrc1 notch filter enable 0 = disabled 1 = enabled it is recommended to enable the notch filter for typical applications.
production data WM5102 w pd, may 2013, rev 4.0 107 register address bit label default description r3827 (0ef3h) isrc 2 ctrl 1 14:11 isrc2_fsh [3:0] 0000 isrc2 high sample rate (sets the higher of the isrc2 sample rates) 0000 = sample_rate_1 0001 = sample_rate_2 0010 = sample_rate_3 1000 = async_sample_rate_1 1001 = async_sample_rate_2 all other codes are reserved. the selected sample rate is valid in the range 8khz to 192khz. the isrc2_fsh and isrc2_fsl fields must both select sample rates referenced to the same clock domain (sysclk or asyncclk). r3828 (0ef4h) isrc 2 ctrl 2 14:11 isrc2_fsl [3:0] 0000 isrc2 low sample rate (sets the lower of the isrc2 sample rates) 0000 = sample_rate_1 0001 = sample_rate_2 0010 = sample_rate_3 1000 = async_sample_rate_1 1001 = async_sample_rate_2 all other codes are reserved. the selected sample rate is valid in the range 8khz to 192khz. the isrc2_fsh and isrc2_fsl fields must both select sample rates referenced to the same clock domain (sysclk or asyncclk). r3829 (0ef5h) isrc 2 ctrl 3 15 isrc2_int1_en a 0 isrc2 int1 enable (interpolation channel 1 path from isrc2_fsl rate to isrc2_fsh rate) 0 = disabled 1 = enabled 14 isrc2_int2_en a 0 isrc2 int2 enable (interpolation channel 2 path from isrc2_fsl rate to isrc2_fsh rate) 0 = disabled 1 = enabled 9 isrc2_dec1_en a 0 isrc2 dec1 enable (decimation channel 1 path from isrc2_fsh rate to isrc2_fsl rate) 0 = disabled 1 = enabled 8 isrc2_dec2_en a 0 isrc2 dec2 enable (decimation channel 2 path from isrc2_fsh rate to isrc2_fsl rate) 0 = disabled 1 = enabled 0 isrc2_notch_ ena 0 isrc2 notch filter enable 0 = disabled 1 = enabled it is recommended to enable the notch filter for typical applications. table 22 digital core isrc control
WM5102 production data w pd, may 2013, rev 4.0 108 dsp firmware control the WM5102 digital core incorporates a progra mmable dsp block, capable of running a wide range of audio enhancement functions. diffe rent firmware configurati ons can be loaded onto the dsp, enabling the WM5102 to be highly customised fo r specific application requirements. examples of the dsp functions include high de finition bass (hdbass?), virtual surround sound (vss), multiband compressor (mbc). note that it is possible to implement more than one type of audio enhancement function on the dsp; the precise co mbination(s) of functions will vary from one firmware configuration to another. in order to use the dsp, the required firmware configuration must first be loaded onto the device by writing the appropriate files to the WM5102 register map. the firmware configuration will comprise program, coefficient and data content. in some case s, the coefficient content must be derived using tools provided in wolfson?s wisce? evaluation board control software. details of how to load the firmware configurati on onto the WM5102 are described below. note that the wisce? evaluation board control software provides support for easy loading of program, coefficient and data content onto the WM5102. please contact your local wolfson representative for more details of the wisce? evaluation board control software. after loading the dsp firmware, the dsp functions must be enabled using the associated register control fields. the audio signal paths connecting to/fr om the dsp are configured as described in the ?digital core? section. note that the dsp firmware must be loaded and enabled before audio signal paths can be enabled. dsp firmware memory control the dsp firmware memory is programmed by writi ng to the registers referenced in table 23. note that the dsp clock must be configured and enabled for the respective dsp block to support read/write access to these registers. the WM5102 program, coefficient and data memory s pace is described in table 23. see ?register map? for a definition of these register addresses. the program firmware parameters are formatted as 40- bit words. for this reason, 3 x 16-bit register addresses are required for each 40-bit word. the coefficient and data firmware parameters are fo rmatted as 24-bit words. for this reason, 2 x 16- bit register addresses are required for each 24-bit word. description register address dsp memory size dsp1 program memory 10_0000h to 10_5fffh (24576 registers) 8192 x 40-bit words coefficient memory 18_0000h to 18_07ffh (2048 registers) 1024 x 24-bit words x data memory 19_0000h to 19_47ffh (18432 registers) 9216 x 24-bit words y data memory 1a_8000h to 1a_97ffh (6144 registers) 3072 x 24-bit words table 23 dsp program, coefficient and data registers clocking is required for any functionality of the dsp, including any register read/write operations associated with dsp firmware loading. the clock source for the dsp is derived from sysclk, which must also be enabled. see ?clocking and sample rates? for details of how to configure sysclk. the dsp clock frequency is selected using the d sp1_clk_sel register. the dsp clock frequency must be less than or equal to the sysclk frequency. if the subsys_max_freq bit is set to ?0?, then the dsp clock frequency is restricted to a maximum of 24.576mhz (or 22.5792mhz), even if a higher rate is selected. the subsys_max_freq should only be set to ?1? when the applicable dcvdd conditi on is satisfied, as described in table 87. the clock source for the dsp bl ock is enabled using dsp1_sys_ena.
production data WM5102 w pd, may 2013, rev 4.0 109 the dsp memory must be enabled for any functionality of the dsp, including any register read/write operations associated with dsp firmware l oading. the dsp memory is controlled using dsp1_mem_ena; this bit is enabled by default. the dsp1_ram_rdy status bits indicate when t he dsp firmware memory registers are ready for read/write access. the dsp ram ready flags are inputs to the interr upt control circuit and c an be used to trigger an interrupt event - see ?interrupts?. the dsp ram ready flags can be output directly on a gpio pin as an external indication of the dsp ram status. see ?general purpose input / output? to configure a gpio pi n for this function. the dsp memory contents are retained during hardware reset and software reset. the dsp memory contents are cleared in sleep mode, or if dcvdd falls below its reset threshold. register address bit label default description r4352 (1100h) dsp1 control 1 4 dsp1_mem_en a 1 dsp1 memory control 0 = disabled 1 = enabled the dsp1 memory control must be enabled for dsp1 firmware register access and also for firmware execution. 2 dsp1_sys_ena 0 dsp1 clock enable 0 = disabled 1 = enabled the dsp1 clock must be enabled for dsp1 firmware register access and also for firmware execution. r4353 (1101h) dsp1 clocking 1 2:0 dsp1_clk_sel [2:0] 000 dsp1 clock frequency select 000 = 6.144mhz (5.6448mhz) 001 = 12.288mhz (11.2896mhz) 010 = 24.576mhz (22.5792mhz) 011 = 49.152mhz (45.1584mhz) the dsp1 clock must be less than or equal to the sysclk frequency. the frequencies in brackets apply for 44.1khz-related sample rates only (ie. sample_rate_n = 01xxx). r4356 (1104h) dsp1 status 1 0 dsp1_ram_rdy 0 dsp1 memory status 0 = not ready 1 = ready table 24 dsp clocking control
WM5102 production data w pd, may 2013, rev 4.0 110 dsp firmware execution after the dsp firmware has been loaded, and the clocks configured, the dsp blocks are enabled using the dsp1_core_ena and dsp1_start register bits. write ?1? to both registers to enable and start the firmware execution. the dsp1_core_ena bit must be set to ?1? to enable dsp firmware execution. note that the usage of the dsp1_start bit may vary depending on the par ticular software that is being executed: in some applications, writing to the dsp1_start bit will not be required. for read/write access to the dsp firmware memory r egisters, the respective firmware execution must be disabled by setting the dsp1_core_ena bit to ?0?. after disabling the dsp (ie. writing dsp1_core_ ena=0), the associated dma must be disabled by setting the dsp1_wdma_buffer_leng th, dsp1_wdma_channel_enable, and dsp1_rdma_channel_enable fields to 0. the audio signal paths connecting to /from the dsp processing blocks are configured as described in the ?digital core? section. note that the dsp firmware must be loaded and enabled before audio signal paths can be enabled. register address bit label default description r4352 (1100h) dsp1 control 1 1 dsp1_core_en a 0 dsp1 enable controls the dsp1 firmware execution 0 = disabled 1 = enabled 0 dsp1_start dsp1 start write ?1? to start dsp1 firmware execution r4400 (1130h) dsp1 wdma config 1 13:0 dsp1_wdma_b uffer_length [13:0] 0000h dsp1 dma buffer length note that this field must be set to 0000h when dsp1 is disabled. r4401 (1131h) dsp1 wdma config 2 7:0 dsp1_wdma_c hannel_enabl e [7:0] 00h dsp1 wdma channel enable note that this field must be set to 00h when dsp1 is disabled. r4404 (1134h) dsp1 rdma config 2 5:0 dsp1_rdma_c hannel_enabl e [5:0] 00h dsp1 rdma channel enable note that this field must be set to 00h when dsp1 is disabled. table 25 dsp firmware execution
production data WM5102 w pd, may 2013, rev 4.0 111 digital audio interface the WM5102 provides three audio interfaces, aif1 , afi2 and aif3. each of these is independently configurable on the respective tr ansmit (tx) and receive (rx) paths . aif1 supports up to 8 channels of input and output signal paths; aif2 and aif3 each support up to 2 channels of input and output signal paths. the data source(s) for the audio interface transmi t (tx) paths can be selected from any of the WM5102 input signal paths, or from the digital core processing functions. t he audio interface receive (rx) paths can be selected as inputs to any of the digital core processing f unctions or digital core outputs. see ?digital core? for details of the digital core routing options. the digital audio interfaces prov ide flexible connectivity for mu ltiple processors and other audio devices. typical connections in clude applications processor, baseband processor and wireless transceiver. note that the slimbus interface also provides digital audio inpu t/output paths, providing options for additional interfaces. a typical configuration is illustrated in figure 38. the audio interfaces aif1, aif2 and aif3 are referenced to dbvdd1, dbvdd2 and dbvdd3 respectively, allowing the WM5102 to connect betw een application sub-systems on different voltage domains. figure 38 typical aif connections in the general case, the digital audio interface uses four pins: ? txdat: data output ? rxdat: data input ? bclk: bit clock, for synchronisation ? lrclk: left/right data alignment clock in master interface mode, the clock signals bclk and lrclk are outputs from the WM5102. in slave mode, these signals are inputs, as illustrated below. as an option, a gpio pin can be configured as txlrclk, ie. the left/right clock for the txdat output. in this case, the lrclk pin is dedicated to the rxdat input, allowing the two sides to be clocked independently.
WM5102 production data w pd, may 2013, rev 4.0 112 four different audio data formats are s upported by the digital audio interface: ? dsp mode a ? dsp mode b ? i2s ? left justified the left justified and dsp-b modes are valid in ma ster mode only (ie. bclk and lrclk are outputs from the WM5102). these modes c annot be supported in slave mode. all four of these modes are msb first. data words are encoded in 2?s complement format. each of the audio interface modes is described in the follo wing sections. refer to the ?signal timing requirements? section for timing information. two variants of dsp mode are supported - ?m ode a? and ?mode b?. mono pcm operation can be supported using the dsp modes. master and slave mode operation the WM5102 digital audio interfaces can operate as a master or slave as shown in figure 39 and figure 40. the associated control bits are descr ibed in ?digital audio interface control?. figure 39 master mode figure 40 slave mode audio data formats the WM5102 digital audio interfaces can be configured to operate in i 2 s, left-justified, dsp-a or dsp-b interface modes. note that left-justified and dsp-b modes are valid in master mode only (ie. bclk and lrclk are outputs from the WM5102). the digital audio interfaces also pr ovide flexibility to support multiple ?slots? of audio data within each lrclk frame. this flexibility allows multiple audio channels to be supported within a single lrclk frame. the data formats described in this section are gener ic descriptions, assuming only one stereo pair of audio samples per lrclk frame. in these cases, the aif is configured to transmit (or receive) in the first available position in each fr ame (ie. the slot 0 position). the options for multi-channel operation are descr ibed in the following section (?aif timeslot configuration?). the audio data modes supported by the WM5102 are de scribed below. note that the polarity of the bclk and lrclk signals can be inverted if requir ed; the following descriptions all assume the default, non-inverted polarity of these signals.
production data WM5102 w pd, may 2013, rev 4.0 113 in dsp mode, the left channel msb is available on either the 1 st (mode b) or 2 nd (mode a) rising edge of bclk following a rising edge of lrclk. right channel data immediately follows left channel data. depending on word length, bclk frequency and samp le rate, there may be unused bclk cycles between the lsb of the right channel data and the next sample. in master mode, the lrclk output will resemble the frame pulse shown in figure 41 and figure 42. in slave mode, it is possible to use any length of fr ame pulse less than 1/fs, providing the falling edge of the frame pulse occurs at least one bclk peri od before the rising edge of the next frame pulse. figure 41 dsp mode a data format figure 42 dsp mode b data format pcm operation is supported in dsp interface mode. WM5102 data that is output on the left channel will be read as mono pcm data by the receiving equipment. mono pcm data received by the WM5102 will be treated as left channel data. this data may be routed to the left/right playback paths using the control fields described in the ?digital core? section. in i 2 s mode, the msb is available on the second ri sing edge of bclk following a lrclk transition. the other bits up to the lsb are then transmi tted in order. depending on word length, bclk frequency and sample rate, there may be unused bclk cycles between the lsb of one sample and the msb of the next. figure 43 i2s data format (assuming n-bit word length)
WM5102 production data w pd, may 2013, rev 4.0 114 in left justified mode, the msb is available on the first rising edge of bclk following a lrclk transition. the other bits up to the lsb are then transmitted in order. depending on word length, bclk frequency and sample rate, there may be unused bclk cycles before each lrclk transition. n n-1 n-2 3 2 1 n n-1 n-2 3 2 1 left channel right channel msb lsb input word length (wl) 1/fs lrclk bclk rxdat/ txdat figure 44 left justified data format (assuming n-bit word length) aif timeslot configuration digital audio interface aif1 supports multi-c hannel operation; up to 8 input (rx) channels and 8 output (tx) channels can be supported simultaneously . a high degree of flexibility is provided to define the position of the audio samples within each lrclk frame; the audio channel samples may be arranged in any order within the frame. aif2 and aif3 also provide flexible configurati on options, but support only 1 stereo input and 1 stereo output pair each. note that, on each interface, all input and output channels must operate at the same sample rate (fs). each of the audio channels can be enabled or disabled independently on the transmit (tx) and receive (rx) signal paths. for each enabled channel, the audio samples are assigned to one timeslot within the lrclk frame. in dsp modes, the timeslots are ordered consecutivel y from the start of the lrclk frame. in i2s and left-justified modes, the even-numbered timeslots are arranged in the first half of the lrclk frame, and the odd-numbered timeslots are arranged in the second half of the frame. the timeslots are assigned independently for the transmi t (tx) and receive (rx) signal paths. there is no requirement to assign every av ailable timeslot to an audio sample; some slots may be unused, if desired. care is required, however, to ensure that no timeslot is allocated to more than one audio channel. the number of bclk cycles within a slot is confi gurable; this is the slot length. the number of valid data bits within a slot is also configurable; this is the word length. the number of bclk cycles per lrclk frame must be configured; it must be ensur ed that there are enough bclk cycles within each lrclk frame to transmit or rece ive all of the enabled audio channels. examples of the aif timeslot configurations are illustrated in figure 45 to figure 48. one example is shown for each of the four possible data formats.
production data WM5102 w pd, may 2013, rev 4.0 115 figure 45 shows an example of dsp mode a fo rmat. four enabled audio channels are shown, allocated to timeslots 0 through to 3. figure 45 dsp mode a example figure 46 shows an example of dsp mode b form at. six enabled audio channels are shown, with timeslots 4 and 5 unsused. figure 46 dsp mode b example
WM5102 production data w pd, may 2013, rev 4.0 116 figure 47 shows an example of i2s format. four enabl ed channels are shown, allocated to timeslots 0 through to 3. figure 47 i2s example figure 48 shows an example of left justif ied format. six enabled channels are shown. figure 48 left justifed example tdm operation between three or more devices the aif operation described above illustrates how multiple audio channels can be interleaved on a single txdat or rxdat pin. the in terface uses time division multip lexing (tdm) to allocate time periods to each of the audio channels in turn. this form of tdm is implemented between two devices , using the electrical connections illustrated in figure 39 or figure 40. it is also possible to implement tdm between thr ee or more devices. this allows one codec to receive audio data from two other devices simultaneous ly on a single audio interface, as illustrated in figure 49, figure 50 and figure 51. the WM5102 provides full support for tdm operati on. the txdat pin can be tri-stated when not transmitting data, in order to allow other devices to transmit on the same wire. the behaviour of the txdat pin is configurable, to allow maximum flexibilit y to interface with other devices in this way. typical configurations of tdm operation between th ree devices are illustrated in figure 49, figure 50 and figure 51.
production data WM5102 w pd, may 2013, rev 4.0 117 figure 49 tdm with WM5102 as master figure 50 tdm with other codec as master figure 51 tdm with processor as master note: the WM5102 is a 24-bit device. if the user operates the WM5102 in 32-bit mode then the 8 lsbs will be ignored on the receiving side and not driven on t he transmitting side. it is therefore recommended to add a pull-down resistor if necessary to the rxdat line and the txdat line in tdm mode.
WM5102 production data w pd, may 2013, rev 4.0 118 digital audio interface control this section describes the configuration of the WM5102 digital audio interface paths. aif1 supports up to 8 input signal paths and up to 8 output signal paths. aif2 and aif3 support up to 2 input and output signal paths each. the digita l audio interfaces aif1, aif2 and aif3 can be configured as master or slave in terfaces; mixed master/slave conf igurations are also possible. each input and output signal path can be independently enabled or disabled. the aif output (tx) and aif input (rx) paths can use a common lrclk fram e clock, or can use separate lrclk signals if required. the digital audio interface supports flexible data formats, selectable word-length, configurable timeslot allocations and tdm tri-state control. aif sample rate control the aif rx inputs may be selected as input to the di gital mixers or signal pr ocessing functions within the WM5102 digital core. the aif tx outputs are derived from the respective output mixers. the sample rate for each digital audio interface ai fn is configured using t he respective aifn_rate register - see table 20 within the ?digital core? section. note that sample rate conversion is required when routing the aif paths to any signal chain that is asynchronous and/or configured for a different sample rate. aif master / slave control the digital audio interfaces can operate in master or slave modes and also in mixed master/slave configurations. in master mode, the bclk and lrclk signals are generated by the WM5102 when any of the respective digital audio interface c hannels is enabled. in slave mode, these outputs are disabled by default to allow another device to drive these pins. master mode is selected on the aifnbclk pin usi ng the aifn_bclk_mstr register bit. in master mode, the aifnbclk signal is generated by the WM5102 when one or more aifn channels is enabled. when the aifn_bclk_frc bit is set in bclk mast er mode, the aifnbclk signal is output at all times, including when none of the aifn channels is enabled. the aifnbclk signal can be inverted in master or slave modes using the aifn_bclk_inv register. master mode is selected on the aifnlrclk pin us ing the aifnrx_lrclk_mstr register bit. in master mode, the aifnrxlrclk signal is generated by the WM5102 when one or more aifn channels is enabled. (note that, when gpion is conf igured as aifntxlrclk, then only the aifn rx channels will cause aifnrxlrclk to be output.) when the aifnrx_lrclk_frc bit is set in lrclk master mode, the aifnrxlrclk signal is output at all times, including when none of the aifn channel s is enabled. note that aifnrxlrclk is derived from aifnbclk, and an internal or external aifnbclk signal must be present to generate aifnrxlrclk. the aifnrxlrclk signal can be inverted in master or slave modes using the aifnrx_lrclk_inv register. under default conditions, the aifn input (rx) and output (tx) paths both use the aifnrxlrclk signal as the frame synchronisation clock. the aifn output (tx) interface can be configured to use a separate frame clock, aifntxlrclk, using the aifntx_lrclk_src bit. the aifntxlrclk function, when used, must be selected on the gpion pin as described in the ?general purpose input / output? section. the aifntxlrclk function can operate in master or slave mode, and is controlled similarly to the aifnrxlrclk function using the r egister bits described in table 26, table 27 and table 28 for aif1, aif2 and aif3 respectively.
production data WM5102 w pd, may 2013, rev 4.0 119 register address bit label default description r1280 (0500h) aif1 bclk ctrl 7 aif1_bclk_inv 0 aif1 audio interface bclk invert 0 = aif1bclk not inverted 1 = aif1bclk inverted 6 aif1_bclk_frc 0 aif1 audio interface bclk output control 0 = normal 1 = aif1bclk always enabled in master mode 5 aif1_bclk_mst r 0 aif1 audio interface bclk master select 0 = aif1bclk slave mode 1 = aif1bclk master mode r1281 (0501h) aif1 tx pin ctrl 3 aif1tx_lrclk_ src 1 aif1 audio interface tx path lrclk select 0 = aif1txlrclk 1 = aif1rxlrclk note that the txlrclk function, when used, must be configured on a gpio pin. 2 aif1tx_lrclk_i nv 0 aif1 audio interface tx path lrclk invert 0 = aif1txlrclk not inverted 1 = aif1txlrclk inverted 1 aif1tx_lrclk_ frc 0 aif1 audio interface tx path lrclk output control 0 = normal 1 = aif1txlrclk always enabled in master mode 0 aif1tx_lrclk_ mstr 0 aif1 audio interface tx path lrclk master select 0 = aif1txlrclk slave mode 1 = aif1txlrclk master mode r1282 (0502h) aif1 rx pin ctrl 2 aif1rx_lrclk_ inv 0 aif1 audio interface lrclk invert 0 = aif1rxlrclk not inverted 1 = aif1rxlrclk inverted 1 aif1rx_lrclk_ frc 0 aif1 audio interface lrclk output control 0 = normal 1 = aif1rxlrclk always enabled in master mode 0 aif1rx_lrclk_ mstr 0 aif1 audio interface lrclk master select 0 = aif1rxlrclk slave mode 1 = aif1rxlrclk master mode table 26 aif1 master / slave control register address bit label default description r1344 (0540h) aif2 bclk ctrl 7 aif2_bclk_inv 0 aif2 audio interface bclk invert 0 = aif2bclk not inverted 1 = aif2bclk inverted 6 aif2_bclk_frc 0 aif2 audio interface bclk output control 0 = normal 1 = aif2bclk always enabled in master mode
WM5102 production data w pd, may 2013, rev 4.0 120 register address bit label default description 5 aif2_bclk_mst r 0 aif2 audio interface bclk master select 0 = aif2bclk slave mode 1 = aif2bclk master mode r1345 (0541h) aif2 tx pin ctrl 3 aif2tx_lrclk_ src 1 aif2 audio interface tx path lrclk select 0 = aif2txlrclk 1 = aif2rxlrclk note that the txlrclk function, when used, must be configured on a gpio pin. 2 aif2tx_lrclk_i nv 0 aif2 audio interface tx path lrclk invert 0 = aif2txlrclk not inverted 1 = aif2txlrclk inverted 1 aif2tx_lrclk_ frc 0 aif2 audio interface tx path lrclk output control 0 = normal 1 = aif2txlrclk always enabled in master mode 0 aif2tx_lrclk_ mstr 0 aif2 audio interface tx path lrclk master select 0 = aif2txlrclk slave mode 1 = aif2txlrclk master mode r1346 (0542h) aif2 px pin ctrl 2 aif2rx_lrclk_ inv 0 aif2 audio interface lrclk invert 0 = aif2rxlrclk not inverted 1 = aif2rxlrclk inverted 1 aif2rx_lrclk_ frc 0 aif2 audio interface lrclk output control 0 = normal 1 = aif2rxlrclk always enabled in master mode 0 aif2rx_lrclk_ mstr 0 aif2 audio interface lrclk master select 0 = aif2rxlrclk slave mode 1 = aif2rxlrclk master mode table 27 aif2 master / slave control register address bit label default description r1408 (0580h) aif3 bclk ctrl 7 aif3_bclk_inv 0 aif3 audio interface bclk invert 0 = aif3bclk not inverted 1 = aif3bclk inverted 6 aif3_bclk_frc 0 aif3 audio interface bclk output control 0 = normal 1 = aif3bclk always enabled in master mode 5 aif3_bclk_mst r 0 aif3 audio interface bclk master select 0 = aif3bclk slave mode 1 = aif3bclk master mode r1409 (0581h) aif3 tx pin ctrl 3 aif3tx_lrclk_ src 1 aif3 audio interface tx path lrclk select 0 = aif3txlrclk 1 = aif3rxlrclk note that the txlrclk function, when used, must be configured on a gpio pin.
production data WM5102 w pd, may 2013, rev 4.0 121 register address bit label default description 2 aif3tx_lrclk_i nv 0 aif3 audio interface tx path lrclk invert 0 = aif3txlrclk not inverted 1 = aif3txlrclk inverted 1 aif3tx_lrclk_ frc 0 aif3 audio interface tx path lrclk output control 0 = normal 1 = aif3txlrclk always enabled in master mode 0 aif3tx_lrclk_ mstr 0 aif3 audio interface tx path lrclk master select 0 = aif3txlrclk slave mode 1 = aif3txlrclk master mode r1410 (0582h) aif3 rx pin ctrl 2 aif3rx_lrclk_ inv 0 aif3 audio interface lrclk invert 0 = aif3rxlrclk not inverted 1 = aif3rxlrclk inverted 1 aif3rx_lrclk_ frc 0 aif3 audio interface lrclk output control 0 = normal 1 = aif3rxlrclk always enabled in master mode 0 aif3rx_lrclk_ mstr 0 aif3 audio interface lrclk master select 0 = aif3rxlrclk slave mode 1 = aif3rxlrclk master mode table 28 aif3 master / slave control aif signal path enable the aif1 interface supports up to 8 input (rx) channels and up to 8 output (tx) channels. each of these channels can be enabled or di sabled using the register bits defined in table 29. the aif2 and aif3 interfaces support up to 2 i nput (rx) channels and up to 2 output (tx) channels. each of these channels can be enabl ed or disabled using the regist er bits defined in table 30 and table 31. the system clock, sysclk, must be confi gured and enabled before any audio path is enabled. the asyncclk may also be required, depending on the pat h configuration. see ?clocking and sample rates? for details of the system clocks. the WM5102 performs automatic checks to conf irm that the sysclk and asyncclk frequencies are high enough to support the commanded signal paths and processing functions. if an attempt is made to enable an aif signal path, and there are insufficient sysclk or asyncclk cycles to support it, then the attempt will be unsuccessful. (note that any signal paths that are already active will not be affected under these circumstances.) the underclocked error conditions can be monitored using the gpio and/or interrupt functions. see ?general purpose input / output? and ?interrupts? for further details. register address bit label default description r1305 (0519h) aif1 tx enables 7 aif1tx8_ena 0 aif1 audio interface tx channel 8 enable 0 = disabled 1 = enabled 6 aif1tx7_ena 0 aif1 audio interface tx channel 7 enable 0 = disabled 1 = enabled
WM5102 production data w pd, may 2013, rev 4.0 122 register address bit label default description 5 aif1tx6_ena 0 aif1 audio interface tx channel 6 enable 0 = disabled 1 = enabled 4 aif1tx5_ena 0 aif1 audio interface tx channel 5 enable 0 = disabled 1 = enabled 3 aif1tx4_ena 0 aif1 audio interface tx channel 4 enable 0 = disabled 1 = enabled 2 aif1tx3_ena 0 aif1 audio interface tx channel 3 enable 0 = disabled 1 = enabled 1 aif1tx2_ena 0 aif1 audio interface tx channel 2 enable 0 = disabled 1 = enabled 0 aif1tx1_ena 0 aif1 audio interface tx channel 1 enable 0 = disabled 1 = enabled r1306 (051ah) aif1 rx enables 7 aif1rx8_ena 0 aif1 audio interface rx channel 8 enable 0 = disabled 1 = enabled 6 aif1rx7_ena 0 aif1 audio interface rx channel 7 enable 0 = disabled 1 = enabled 5 aif1rx6_ena 0 aif1 audio interface rx channel 6 enable 0 = disabled 1 = enabled 4 aif1rx5_ena 0 aif1 audio interface rx channel 5 enable 0 = disabled 1 = enabled 3 aif1rx4_ena 0 aif1 audio interface rx channel 4 enable 0 = disabled 1 = enabled 2 aif1rx3_ena 0 aif1 audio interface rx channel 3 enable 0 = disabled 1 = enabled 1 aif1rx2_ena 0 aif1 audio interface rx channel 2 enable 0 = disabled 1 = enabled 0 aif1rx1_ena 0 aif1 audio interface rx channel 1 enable 0 = disabled 1 = enabled table 29 aif1 signal path enable
production data WM5102 w pd, may 2013, rev 4.0 123 register address bit label default description r1369 (0559h) aif2 tx enables 1 aif2tx2_ena 0 aif2 audio interface tx channel 2 enable 0 = disabled 1 = enabled 0 aif2tx1_ena 0 aif2 audio interface tx channel 1 enable 0 = disabled 1 = enabled r1370 (055ah) aif2 rx enables 1 aif2rx2_ena 0 aif2 audio interface rx channel 2 enable 0 = disabled 1 = enabled 0 aif2rx1_ena 0 aif2 audio interface rx channel 1 enable 0 = disabled 1 = enabled table 30 aif2 signal path enable register address bit label default description r1433 (0599h) aif3 tx enables 1 aif3tx2_ena 0 aif3 audio interface tx channel 2 enable 0 = disabled 1 = enabled 0 aif3tx1_ena 0 aif3 audio interface tx channel 1 enable 0 = disabled 1 = enabled r1434 (059ah) aif3 rx enables 1 aif3rx2_ena 0 aif3 audio interface rx channel 2 enable 0 = disabled 1 = enabled 0 aif3rx1_ena 0 aif3 audio interface rx channel 1 enable 0 = disabled 1 = enabled table 31 aif3 signal path enable
WM5102 production data w pd, may 2013, rev 4.0 124 aif bclk and lrclk control the aifnbclk frequency is selected by the aifn_b clk_freq register. for each value of this register, the actual frequency depends upon whether ai fn is configured for a 48khz-related sample rate or a 44.1khz-related sample rate, as described below. if aifn_rate<1000 (see table 20), then aifn is re ferenced to the sysclk clocking domain and the applicable frequency depends upon the sample_rate _1, sample_rate_2 or sample_rate_3 registers. if aifn_rate 1000, then aifn is referenced to the asyncclk clocking domain and the applicable frequency depends upon the async_sample_rate_1 or async_sample_rate_2 registers. the selected aifnbclk rate must be less than or equal to sysclk/2, or asyncclk/2, as applicable. see ?clocking and sample rates? for details of sysclk and asyncclk domains, and the associated control registers. the aifnrxlrclk frequency is controlled relative to aifnbclk by the aifnrx_bcpf divider. under default conditions, the aifn input (rx) and output (tx) paths both use the aifnrxlrclk signal as the frame synchronisation clock. the aifn output (tx) interface can be configured to use a separate frame clock, aifntxlrclk, using the aifntx_lrclk_src bit, as described in table 26, table 27 and table 28 for aif1, aif2 and aif3 respectively. when the gpion pin is configur ed as aifntxlrclk, then the aifntxlrclk frequency is controlled relative to aifnbclk by the aifntx_bcpf divider . see ?general purpose input / output? for details of how to configure the gp io1, gpio2 or gpio3 pins. note that the bclk rate must be configured in master or slave modes, using the aifn_bclk_freq registers. the lrclk rate(s) only require to be configured in master mode.
production data WM5102 w pd, may 2013, rev 4.0 125 register address bit label default description r1280 (0500h) aif1 bclk ctrl 4:0 aif1_bclk_fre q [4:0] 01100 aif1bclk rate 00000 = reserved 00001 = 48khz (44.1khz) 00010 = 64khz (58.8khz) 00011 = 96khz (88.2khz) 00100 = 128khz (117.6khz) 00101 = 192khz (176.4khz) 00110 = 256khz (235.2khz) 00111 = 384khz (352.8khz) 01000 = 512khz (470.4khz) 01001 = 768khz (705.6khz) 01010 = 1.024mhz (940.8khz) 01011 = 1.536mhz (1.4112mhz) 01100 = 2.048mhz (1.8816mhz) 01101 = 3.072mhz (2.8824mhz) 01110 = 4.096mhz (3.7632mhz) 01111 = 6.144mhz (5.6448mhz) 10000 = 8.192mhz (7.5264mhz) 10001 = 12.288mhz (11.2896mhz) the frequencies in brackets apply for 44.1khz-related sample rates only. if aif1_rate<1000, then aif1 is referenced to sysclk and the 44.1khz- related frequencies apply if sample_rate_n = 01xxx. if aif1_rate>=1000, then aif1 is referenced to asyncclk and the 44.1khz-related frequencies apply if async_sample_rate_n = 01xxx. the aif1bclk rate must be less than or equal to sysclk/2, or asyncclk/2, as applicable. r1285 (0505h) aif1 tx bclk rate 12:0 aif1tx_bcpf [12:0] 0040h aif1txlrclk rate this register selects the number of bclk cycles per aif1txlrclk frame. aif1txlrclk clock = aif1bclk / aif1tx_bcpf integer (lsb = 1), valid from 8..8191 r1286 (0506h) aif1 tx bclk rate 12:0 aif1rx_bcpf [12:0] 0040h aif1rxlrclk rate this register selects the number of bclk cycles per aif1rxlrclk frame. aif1rxlrclk clock = aif1bclk / aif1rx_bcpf integer (lsb = 1), valid from 8..8191 table 32 aif1 bclk and lrclk control
WM5102 production data w pd, may 2013, rev 4.0 126 register address bit label default description r1344 (0540h) aif2 bclk ctrl 4:0 aif2_bclk_fre q [4:0] 01100 aif2bclk rate 00000 = reserved 00001 = 48khz (44.1khz) 00010 = 64khz (58.8khz) 00011 = 96khz (88.2khz) 00100 = 128khz (117.6khz) 00101 = 192khz (176.4khz) 00110 = 256khz (235.2khz) 00111 = 384khz (352.8khz) 01000 = 512khz (470.4khz) 01001 = 768khz (705.6khz) 01010 = 1.024mhz (940.8khz) 01011 = 1.536mhz (1.4112mhz) 01100 = 2.048mhz (1.8816mhz) 01101 = 3.072mhz (2.8824mhz) 01110 = 4.096mhz (3.7632mhz) 01111 = 6.144mhz (5.6448mhz) 10000 = 8.192mhz (7.5264mhz) 10001 = 12.288mhz (11.2896mhz) the frequencies in brackets apply for 44.1khz-related sample rates only. if aif2_rate<1000, then aif2 is referenced to sysclk and the 44.1khz- related frequencies apply if sample_rate_n = 01xxx. if aif2_rate>=1000, then aif2 is referenced to asyncclk and the 44.1khz-related frequencies apply if async_sample_rate_n = 01xxx. the aif2bclk rate must be less than or equal to sysclk/2, or asyncclk/2, as applicable. r1349 (0545h) aif2 tx bclk rate 12:0 aif2tx_bcpf [12:0] 0040h aif2txlrclk rate this register selects the number of bclk cycles per aif2txlrclk frame. aif2txlrclk clock = aif2bclk / aif2tx_bcpf integer (lsb = 1), valid from 8..8191 r1350 (0546h) aif2 rx bclk rate 12:0 aif2rx_bcpf [12:0] 0040h aif2rxlrclk rate this register selects the number of bclk cycles per aif2rxlrclk frame. aif2rxlrclk clock = aif2bclk / aif2rx_bcpf integer (lsb = 1), valid from 8..8191 table 33 aif2 bclk and lrclk control
production data WM5102 w pd, may 2013, rev 4.0 127 register address bit label default description r1408 (0580h) aif3 bclk ctrl 4:0 aif3_bclk_fre q [4:0] 01100 aif3bclk rate 00000 = reserved 00001 = 48khz (44.1khz) 00010 = 64khz (58.8khz) 00011 = 96khz (88.2khz) 00100 = 128khz (117.6khz) 00101 = 192khz (176.4khz) 00110 = 256khz (235.2khz) 00111 = 384khz (352.8khz) 01000 = 512khz (470.4khz) 01001 = 768khz (705.6khz) 01010 = 1.024mhz (940.8khz) 01011 = 1.536mhz (1.4112mhz) 01100 = 2.048mhz (1.8816mhz) 01101 = 3.072mhz (2.8824mhz) 01110 = 4.096mhz (3.7632mhz) 01111 = 6.144mhz (5.6448mhz) 10000 = 8.192mhz (7.5264mhz) 10001 = 12.288mhz (11.2896mhz) the frequencies in brackets apply for 44.1khz-related sample rates only. if aif3_rate<1000, then aif3 is referenced to sysclk and the 44.1khz- related frequencies apply if sample_rate_n = 01xxx. if aif3_rate>=1000, then aif3 is referenced to asyncclk and the 44.1khz-related frequencies apply if async_sample_rate_n = 01xxx. the aif3bclk rate must be less than or equal to sysclk/2, or asyncclk/2, as applicable. r1413 (0585h) aif3 tx bclk rate 12:0 aif3tx_bcpf [12:0] 0040h aif3txlrclk rate this register selects the number of bclk cycles per aif3txlrclk frame. aif3txlrclk clock = aif3bclk / aif3tx_bcpf integer (lsb = 1), valid from 8..8191 r1414 (0586h) aif3 rx bclk rate 12:0 aif3rx_bcpf [12:0] 0040h aif3rxlrclk rate this register selects the number of bclk cycles per aif3rxlrclk frame. aif3rxlrclk clock = aif3bclk / aif3rx_bcpf integer (lsb = 1), valid from 8..8191 table 34 aif3 bclk and lrclk control the WM5102 performs automatic checks to confirm that each aif is configured with valid settings. invalid settings include conditions where one or more audio channel timeslots are in conflict. if an aif1 configuration error, aif2 configuration error or aif3 configur ation error is detected, this can be indicated using the gpio and/or interrupt f unctions. see ?general purpose input / output? and ?interrupts? for further details.
WM5102 production data w pd, may 2013, rev 4.0 128 aif digital audio data control the register bits controlling the audio data format, wo rd lengths and slot confi gurations for aif1, aif2 and aif3 are described in table 35, table 36 and table 37 respectively. note that left-justified and dsp-b modes are valid in master mode only (ie. bclk and lrclk are outputs from the WM5102). the aifn slot length is the number of bclk cycles in one timeslot within the overall lrclk frame. the word length is the number of valid data bits with in each timeslot. (if the word length is less than the slot length, then there will be unused bclk cycles at the end of each timeslot.) the aifn word length and slot length is independently selectable for the input (rx) and output (tx) paths. for each aif input (rx) and aif output (tx) channel, the position of the audio data sample within the lrclk frame is configurable. the _slot registers def ine the timeslot position of the audio sample for the associated audio channel. valid selections are slot 0 upwards. the timeslots are numbered as illustrated in figure 45 through to figure 48. note that, in dsp modes, the timeslots are ordered c onsecutively from the start of the lrclk frame. in i2s and left-justified modes, the even-numbered ti meslots are arranged in the first half of the lrclk frame, and the odd-numbered timeslots are arranged in the second half of the frame. register address bit label default description r1284 (0504h) aif1 format 2:0 aif1_fmt [2:0] 000 aif1 audio interface format 000 = dsp mode a 001 = dsp mode b 010 = i 2 s mode 011 = left justified mode other codes are reserved r1287 (0507h) aif1 frame ctrl 1 13:8 aif1tx_wl [5:0] 18h aif1 tx word length (number of valid data bits per slot) integer (lsb = 1); valid from 16 to 32 7:0 aif1tx_slot_l en [7:0] 18h aif1 tx slot length (number of bclk cycles per slot) integer (lsb = 1); valid from 16 to 128 r1288 (0508h) aif1 frame ctrl 2 13:8 aif1rx_wl [5:0] 18h aif1 rx word length (number of valid data bits per slot) integer (lsb = 1); valid from 16 to 32 7:0 aif1rx_slot_l en [7:0] 18h aif1 rx slot length (number of bclk cycles per slot) integer (lsb = 1); valid from 16 to 128 r1289 (0509h) to r1296 (0510h) 5:0 aif1tx1_slot [5:0] 0h aif1 tx channel n slot position defines the tx timeslot position of the channel n audio sample integer (lsb=1); valid from 0 to 63 5:0 aif1tx2_slot [5:0] 1h 5:0 aif1tx3_slot [5:0] 2h 5:0 aif1tx4_slot [5:0] 3h 5:0 aif1tx5_slot [5:0] 4h 5:0 aif1tx6_slot [5:0] 5h 5:0 aif1tx7_slot [5:0] 6h 5:0 aif1tx8_slot [5:0] 7h
production data WM5102 w pd, may 2013, rev 4.0 129 register address bit label default description r1297 (0511h) to r1304 (0518h) 5:0 aif1rx1_slot [5:0] 0h aif1 rx channel n slot position defines the rx timeslot position of the channel n audio sample integer (lsb=1); valid from 0 to 63 5:0 aif1rx2_slot [5:0] 1h 5:0 aif1rx3_slot [5:0] 2h 5:0 aif1rx4_slot [5:0] 3h 5:0 aif1rx5_slot [5:0] 4h 5:0 aif1rx6_slot [5:0] 5h 5:0 aif1rx7_slot [5:0] 6h 5:0 aif1rx8_slot [5:0] 7h table 35 aif1 digital audio data control register address bit label default description r1348 (0544h) aif2 format 2:0 aif2_fmt [2:0] 000 aif2 audio interface format 000 = dsp mode a 001 = dsp mode b 010 = i 2 s mode 011 = left justified mode other codes are reserved r1351 (0547h) aif2 frame ctrl 1 13:8 aif2tx_wl [5:0] 18h aif2 tx word length (number of valid data bits per slot) integer (lsb = 1); valid from 16 to 32 7:0 aif2tx_slot_l en [7:0] 18h aif2 tx slot length (number of bclk cycles per slot) integer (lsb = 1); valid from 16 to 128 r1352 (0548h) aif2 frame ctrl 2 13:8 aif2rx_wl [5:0] 18h aif2 rx word length (number of valid data bits per slot) integer (lsb = 1); valid from 16 to 32 7:0 aif2rx_slot_l en [7:0] 18h aif2 rx slot length (number of bclk cycles per slot) integer (lsb = 1); valid from 16 to 128 r1353 (0549h) aif2 frame ctrl 3 5:0 aif2tx1_slot [5:0] 0h aif2 tx channel 1 slot position defines the tx timeslot position of the channel 1 audio sample integer (lsb=1); valid from 0 to 63 r1354 (054ah) aif2 frame ctrl 4 5:0 aif2tx2_slot [5:0] 1h aif2 tx channel 2 slot position defines the tx timeslot position of the channel 2 audio sample integer (lsb=1); valid from 0 to 63 r1361 (0551h) aif2 frame ctrl 11 5:0 aif2rx1_slot [5:0] 0h aif2 rx channel 1 slot position defines the rx timeslot position of the channel 1 audio sample integer (lsb=1); valid from 0 to 63
WM5102 production data w pd, may 2013, rev 4.0 130 register address bit label default description r1362 (0552h) aif2 frame ctrl 12 5:0 aif2rx2_slot [5:0] 1h aif2 rx channel 2 slot position defines the rx timeslot position of the channel 2 audio sample integer (lsb=1); valid from 0 to 63 table 36 aif2 digital audio data control register address bit label default description r1412 (0584h) aif3 format 2:0 aif3_fmt [2:0] 000 aif3 audio interface format 000 = dsp mode a 001 = dsp mode b 010 = i 2 s mode 011 = left justified mode other codes are reserved r1415 (0587h) aif3 frame ctrl 1 13:8 aif3tx_wl [5:0] 18h aif3 tx word length (number of valid data bits per slot) integer (lsb = 1); valid from 16 to 32 7:0 aif3tx_slot_l en [7:0] 18h aif3 tx slot length (number of bclk cycles per slot) integer (lsb = 1); valid from 16 to 128 r1416 (0588h) aif3 frame ctrl 2 13:8 aif3rx_wl [5:0] 18h aif3 rx word length (number of valid data bits per slot) integer (lsb = 1); valid from 16 to 32 7:0 aif3rx_slot_l en [7:0] 18h aif3 rx slot length (number of bclk cycles per slot) integer (lsb = 1); valid from 16 to 128 r1417 (0589h) aif3 frame ctrl 3 5:0 aif3tx1_slot [5:0] 0h aif3 tx channel 1 slot position defines the tx timeslot position of the channel 1 audio sample integer (lsb=1); valid from 0 to 63 r1418 (058ah) aif3 frame ctrl 4 5:0 aif3tx2_slot [5:0] 1h aif3 tx channel 2 slot position defines the tx timeslot position of the channel 2 audio sample integer (lsb=1); valid from 0 to 63 r1425 (0591h) aif3 frame ctrl 11 5:0 aif3rx1_slot [5:0] 0h aif3 rx channel 1 slot position defines the rx timeslot position of the channel 1 audio sample integer (lsb=1); valid from 0 to 63 r1426 (0592h) aif3 frame ctrl 12 5:0 aif3rx2_slot [5:0] 1h aif3 rx channel 2 slot position defines the rx timeslot position of the channel 2 audio sample integer (lsb=1); valid from 0 to 63 table 37 aif3 digital audio data control the WM5102 performs automatic checks to confirm t hat each aif is configured with valid settings. invalid settings include conditions where one or more audio channel timeslots are in conflict. if an aif1 configuration error, aif2 configuration error or aif3 configur ation error is detected, this can be indicated using the gpio and/or interrupt f unctions. see ?general purpose input / output? and ?interrupts? for further details.
production data WM5102 w pd, may 2013, rev 4.0 131 aif tdm and tri-state control the aifn output pins are tri-stated when the aifn_tri register is set. note that, when a gpion pin is configured as a gpio, this pin is not affected by the respective aifn_tri register. see ?general purpose input / output? to configure the gpio pins. under default conditions, the aifntxdat output is held at logic 0 when the WM5102 is not transmitting data (ie. during timeslots that ar e not enabled for output by the WM5102). when the aifntx_dat_tri register is set, the WM5102 tri- states the respective aifntxdat pin when not transmitting data, allowing other devices to drive the aifntxdat connection. register address bit label default description r1281 (0501h) aif1 tx pin ctrl 5 aif1tx_dat_tr i 0 aif1txdat tri-state control 0 = logic 0 during unused timeslots 1 = tri-stated during unused timeslots r1283 (0503h) aif1 rate ctrl 6 aif1_tri 0 aif1 audio interface tri-state control 0 = normal 1 = aif1 outputs are tri-stated note that the gpio1 pin is only tri-stated by this register when it is configured as aif1txlrclk. table 38 aif1 tdm and tri-state control register address bit label default description r1345 (0541h) aif2 tx pin ctrl 5 aif2tx_dat_tr i 0 aif2txdat tri-state control 0 = logic 0 during unused timeslots 1 = tri-stated during unused timeslots r1347 (0543h) aif2 rate ctrl 6 aif2_tri 0 aif2 audio interface tri-state control 0 = normal 1 = aif2 outputs are tri-stated note that the gpio2 pin is only tri-stated by this register when it is configured as aif2txlrclk. table 39 aif2 tdm and tri-state control register address bit label default description r1409 (0581h) aif3 tx pin ctrl 5 aif3tx_dat_tr i 0 aif3txdat tri-state control 0 = logic 0 during unused timeslots 1 = tri-stated during unused timeslots r1411 (0583h) aif3 rate ctrl 6 aif3_tri 0 aif3 audio interface tri-state control 0 = normal 1 = aif3 outputs are tri-stated note that the gpio3 pin is only tri-stated by this register when it is configured as aif3txlrclk. table 40 aif3 tdm and tri-state control
WM5102 production data w pd, may 2013, rev 4.0 132 aif digital pull-up and pull-down the WM5102 provides integrated pull-up and pull- down resistors on each of the aifnlrclk, aifnbclk and aifnrxdat pins. this provides a flexible capability for interfacing with other devices. each of the pull-up and pull-down resistors can be configured independently usi ng the register bits described in table 41, table 42 and table 43. note that if the pull-up and pull-down are both enabled for any pin, then the pull-up and pull-down will be disabled. register address bit label default description r3107 (0c23h) misc pad ctrl 4 5 aif1lrclk_pu 0 aif1lrclk pull-up control 0 = disabled 1 = enabled 4 aif1lrclk_pd 0 aif1lrclk pull-down control 0 = disabled 1 = enabled 3 aif1bclk_pu 0 aif1bclk pull-up control 0 = disabled 1 = enabled 2 aif1bclk_pd 0 aif1bclk pull-down control 0 = disabled 1 = enabled 1 aif1rxdat_pu 0 aif1rxdat pull-up control 0 = disabled 1 = enabled 0 aif1rxdat_pd 0 aif1rxdat pull-down control 0 = disabled 1 = enabled table 41 aif1 digital pull-up and pull-down control register address bit label default description r3108 (0c24h) misc pad ctrl 5 5 aif2lrclk_pu 0 aif2lrclk pull-up control 0 = disabled 1 = enabled 4 aif2lrclk_pd 0 aif2lrclk pull-down control 0 = disabled 1 = enabled 3 aif2bclk_pu 0 aif2bclk pull-up control 0 = disabled 1 = enabled 2 aif2bclk_pd 0 aif2bclk pull-down control 0 = disabled 1 = enabled 1 aif2rxdat_pu 0 aif2rxdat pull-up control 0 = disabled 1 = enabled 0 aif2rxdat_pd 0 aif2rxdat pull-down control 0 = disabled 1 = enabled table 42 aif2 digital pull-up and pull-down control
production data WM5102 w pd, may 2013, rev 4.0 133 register address bit label default description r3109 (0c25h) misc pad ctrl 6 5 aif3lrclk_pu 0 aif3lrclk pull-up control 0 = disabled 1 = enabled 4 aif3lrclk_pd 0 aif3lrclk pull-down control 0 = disabled 1 = enabled 3 aif3bclk_pu 0 aif3bclk pull-up control 0 = disabled 1 = enabled 2 aif3bclk_pd 0 aif3bclk pull-down control 0 = disabled 1 = enabled 1 aif3rxdat_pu 0 aif3rxdat pull-up control 0 = disabled 1 = enabled 0 aif3rxdat_pd 0 aif3rxdat pull-down control 0 = disabled 1 = enabled table 43 aif3 digital pull-up and pull-down control
WM5102 production data w pd, may 2013, rev 4.0 134 slimbus interface the WM5102 features a mipi-compliant slimbus in terface, providing 8 channels of audio input and 8 channels of audio output. mixed audio sample rates are supported on the slimbus interface. the slimbus interface also supports read/writ e access to the WM5102 control registers. the slimbus interface on WM5102 comprises an in terface device, framer device, and generic device. a maximum of 16 ports can be configured, providing up to 8 input (rx) channels and up to 8 output (tx) channels. the audio paths associated with the slimbus interfac e are described in the ?digital core? section. the slimbus interface supports read/write access to the WM5102 control registers, as described later in this section. the slimbus clocking rate and channel allocations are controlled by the manager device. the message channel and data channel bandwidth may be dynamically adjusted according to the application requirements. note that the manager device functions are not implemented on the WM5102, and these bandwidth allocation requirem ents are outside the scope of this datasheet. slimbus device parameters the enumeration address of each device within t he slimbus interface is derived from the parameters noted in table 44. description manufacturer id product code device id instance value enumeration address interface 0x012f 0x5102 0x7f 0x00 012f_5102_7f00 framer 0x012f 0x5102 0x55 0x00 012f_5102_5500 generic 0x012f 0x 5102 0x00 0x00 012f_5102_0000 table 44 slimbus device parameters the WM5102 slimbus interface supports up to 8 input (rx) channels and up to 8 output (tx) channels. the slimbus port numbers for thes e audio channels are detailed in table 45. WM5102 channel slimbus port number WM5102 channel slimbus port number rx channel 1 0 tx channel 1 8 rx channel 2 1 tx channel 2 9 rx channel 3 2 tx channel 3 10 rx channel 4 3 tx channel 4 11 rx channel 5 4 tx channel 5 12 rx channel 6 5 tx channel 6 13 rx channel 7 6 tx channel 7 14 rx channel 8 7 tx channel 8 15 table 45 slimbus port numbers slimbus sample rate control the slimbus rx inputs may be selected as input to the digital mixers or si gnal processing functions within the WM5102 digital core. the slimbus tx outputs are derived from the respective output mixers. the sample rate for each slimbus channel is configured using the slimrxn_rate and slimtxn_rate registers - see table 20 within the ?digital core? section. note that the slimbus interface provides simultaneous support for sysclk-referenced and asyncclk-referenced sample rates on different channels. for example, 48khz and 44.1khz slimbus audio paths can be simultaneously supported. sample rate conversion is required when routing the slimbus paths to any signal chain that is asynchronous and/or configured for a different sample rate.
production data WM5102 w pd, may 2013, rev 4.0 135 slimbus signal path enable the slimbus interface supports up to 8 input (r x) channels and up to 8 output (tx) channels. each of these channels can be enabled or disabled using the register bits defined in table 46. note that the slimbus audio channels can onl y be supported when the corresponding ports have been enabled by the manager device. the status bi ts in registers r1527 and r1528 indicate the status of each of the slimbus ports. the system clock, sysclk, must be confi gured and enabled before any audio path is enabled. the asyncclk may also be required, depending on the pat h configuration. see ?clocking and sample rates? for details of the system clocks. the WM5102 performs automatic checks to conf irm that the sysclk and asyncclk frequencies are high enough to support the commanded signal paths and processing functions. if an attempt is made to enable a slimbus signal path, and there ar e insufficient sysclk or asyncclk cycles to support it, then the attempt will be unsuccessful. (note that any signal paths that are already active will not be affected under these circumstances.) the underclocked error conditions can be monitored using the gpio and/or interrupt functions. see ?general purpose input / output? and ?interrupts? for further details. register address bit label default description r1525 (05f5h) slimbus rx channel enable 7 slimrx8_ena 0 slimbus rx channel n enable 0 = disabled 1 = enabled 6 slimrx7_ena 0 5 slimrx6_ena 0 4 slimrx5_ena 0 3 slimrx4_ena 0 2 slimrx3_ena 0 1 slimrx2_ena 0 0 slimrx1_ena 0 r1526 (05f6h) slimbus tx channel enable 7 slimtx8_ena 0 slimbus tx channel n enable 0 = disabled 1 = enabled 6 slimtx7_ena 0 5 slimtx6_ena 0 4 slimtx5_ena 0 3 slimtx4_ena 0 2 slimtx3_ena 0 1 slimtx2_ena 0 0 slimtx1_ena 0 r1527 (05f7h) slimbus rx port status 7 slimrx8_port_sts 0 slimbus rx channel n port status (read only) 0 = disabled 1 = configured and active 6 slimrx7_port_sts 0 5 slimrx6_port_sts 0 4 slimrx5_port_sts 0 3 slimrx4_port_sts 0 2 slimrx3_port_sts 0 1 slimrx2_port_sts 0 0 slimrx1_port_sts 0 r1528 (05f8h) slimbus tx port status 7 slimtx8_port_sts 0 slimbus tx channel n port status (read only) 0 = disabled 1 = configured and active 6 slimtx7_port_sts 0 5 slimtx6_port_sts 0 4 slimtx5_port_sts 0 3 slimtx4_port_sts 0 2 slimtx3_port_sts 0 1 slimtx2_port_sts 0 0 slimtx1_port_sts 0 table 46 slimbus signal path enable
WM5102 production data w pd, may 2013, rev 4.0 136 slimbus control register access control register access is supported via the slimbus interface. full read/write access to all registers is possible, via the ?user value el ements? portion of the value map. register write operations are implemented usi ng the ?change_value? message. a maximum of two messages may be required, depending on circum stances: the first ?change_value? message selects the register page (bits [23:8] of the cont rol register address); the second message contains the data and bits [7:0] of the register address. the first message may be omitted if the register page is unchanged from the previous read or write operation. the associated parameters are described in table 47 and table 48, for the generic case of writing the value 0xvvvv to control register address 0x yyyyzz. write message 1 ? change_value parameter value description source address 0xff identifies the manager device as the message source, using the 8-bit logical address. the value is always 0xff. destination address 0xll ?ll? is t he 8-bit logical address of the message destination (ie. the WM5102 slimbus interface device). the value is assigned by the slimbus manager device. access mode 0b1 selects byte-based access mode. byte address 0x800 identifies the user value element for selecting the control register page address. slice size 0b001 selects 2-byte slice size value update 0x yyyy ?yyyy? is bits [23:8] of the applicable control register address. table 47 register write message (1) write message 2 ? change_value parameter value description source address 0xff identifies the manager device as the message source, using the 8-bit logical address. the value is always 0xff. destination address 0xll ?ll? is t he 8-bit logical address of the message destination (ie. the WM5102 slimbus interface device). the value is assigned by the slimbus manager device. access mode 0b1 selects byte-based access mode. byte address 0xuuu specifies the value map address, calculated as 0xa00 + (2 x 0xzz), where ?zz? is bits [7:0] of the applicable control register address. slice size 0b001 selects 2-byte slice size value update 0xvvvv ?vvvv? is the 16-bit data to be written. table 48 register write message (2) note that the first message may be omitted if its contents are unchanged from the previous change_value message sent to the WM5102.
production data WM5102 w pd, may 2013, rev 4.0 137 register read operations are implemented us ing the ?change_value? and ?request_value? messages. a maximum of two messages may be required, depending on circumstances: the ?change_value? message selects the register page (b its [23:8] of the control register address); the ?request_value? message contains bits [7:0] of the register address. the first message may be omitted if the register page is unchanged from the previous read or write operation. the associated parameters are described in table 49 and table 50, for the generic case of reading the contents of control register address 0x yyyyzz. read message 1 ? change_value parameter value description source address 0xff identifies the manager device as the message source, using the 8-bit logical address. the value is always 0xff. destination address 0xll ?ll? is t he 8-bit logical address of the message destination (ie. the WM5102 slimbus interface device). the value is assigned by the slimbus manager device. access mode 0b1 selects byte-based access mode. byte address 0x800 identifies the user value element for selecting the control register page address. slice size 0b001 selects 2-byte slice size value update 0x yyyy ?yyyy? is bits [23:8] of the applicable control register address. table 49 register read message (1) read message 2 ? request_value parameter value description source address 0xff identifies the manager device as the message source, using the 8-bit logical address. the value is always 0xff. destination address 0xll ?ll? is t he 8-bit logical address of the message destination (ie. the WM5102 slimbus interface device). the value is assigned by the slimbus manager device. access mode 0b1 selects byte-based access mode. byte address 0xuuu specifies the value map address, calculated as 0xa00 + (2 x 0xzz), where ?zz? is bits [7:0] of the applicable control register address. slice size 0b001 selects 2-byte slice size transaction id 0xtttt ?tttt? is the 16-bit transaction id for the message. the value is assigned by the slimbus manager device. table 50 register read message (2) note that the first message may be omitted if its contents are unchanged from the previous change_value message sent to the WM5102. the WM5102 will respond to the register read comm ands in accordance with the normal slimbus protocols. note that the WM5102 assumes that sufficient contro l space slots are available in which to provide its response before the next request_value message is received. the WM5102 response is made using a reply_value message; the slimbus manager should wait until the reply_value message has been received before sending the next request_value message. if additional request_value message(s) are received befor e the WM5102 response has been made, then the earlier request_value message(s) will be ignored (ie. only the last request_value message will be serviced)
WM5102 production data w pd, may 2013, rev 4.0 138 slimbus clocking control the clock frequency of the slimbus interface is not fixed, and may be set according to the application requirements. the clock frequency can be re configured dynamically as required. the WM5102 slimbus interface includes a framer de vice. when configured as the active framer, the slimbus clock (slimclk) is an output from t he WM5102. at other times, slimclk is an input. the framer function can be transferred from one device to another; this is known as framer handover, and is controlled by the manager device. the supported root frequencies in active fram er mode are 24.576mhz or 22.5792mhz only. at other times, the supported root frequencies are as defined in the mipi alliance specification for slimbus. under normal operating conditions, the slimbus inte rface operates with a fixed root frequency (rf); dynamic updates to the bus rate are applied using a selectable clock gear (cg) function. the root frequency and the clock gear setting are controlled by the manager device; these parameters are transmitted in every slimbus super frame to all devices on the bus. in gear 10 (the highest clock gear setting), the slimclk input (or output) frequency is equal to the root frequency. in lower gears, the slimclk fr equency is reduced by increasing powers of 2. the clock gear definition is shown in table 51. note that 24.576mhz root frequency is an example only; other frequencies are also supported. clock gear description slimclk frequency (assuming 24.576mhz root frequency) 10 divide by 1 24.576mhz 9 divide by 2 12.288mhz 8 divide by 4 6.144mhz 7 divide by 8 3.072mhz 6 divide by 16 1.536mhz 5 divide by 32 768khz 4 divide by 64 384khz 3 divide by 128 192khz 2 divide by 256 96khz 1 divide by 512 48khz table 51 slimbus clock gear selection when the WM5102 is the active framer, the slimcl k output is synchronised to the sysclk or asyncclk system clock, as selected by the slimclk_src register bit. the applicable system clock must be enabled, and configured at the slimbus root frequency, whenever the WM5102 is the active framer. see ?c locking and sample rates? for details of the sysclk and asyncclk system clocks. when the WM5102 is not configured as the active framer device, then the slimclk input can be used to provide a reference source for the frequency locked loops (flls). the frequency of this reference is controlled using the slimclk_re f_gear register, as described in table 52. the slimbus clock reference is generated usi ng an adaptive divider on the slimclk input. the divider automatically adapts to the slimbus clock gear (cg). note that, if the clock gear (cg) on the bus is lower than the slimclk_ref_gear, then the selected reference frequency cannot be supported, and the slimbus clock reference is disabled. the slimbus clock reference is selected as input to the flls using the flln_refclk_src registers. see ?clocking and sample rates? fo r details of system clocking and the flls.
production data WM5102 w pd, may 2013, rev 4.0 139 register address bit label default description r1507 (05e3h) slimbus framer ref gear 4 slimclk_src 0 slimbus clock source selects the slimbus reference clock in active framer mode. 0 = sysclk 1 = asyncclk note that the applicable clock must be enabled, and configured at the slimbus root frequency, in active framer mode. 3:0 slimclk_ref_ gear [3:0] 4h slimbus clock reference control. sets the slimbus reference clock relative to the slimbus root frequency (rf). 0h = reserved 1h = gear 1 (rf / 512) 2h = gear 2 (rf / 256) 3h = gear 3 (rf / 128) 4h = gear 4 (rf / 64) 5h = gear 5 (rf / 32) 6h = gear 6 (rf / 16) 7h = gear 7 (rf / 8) 8h = gear 8 (rf / 4) 9h = gear 9 (rf / 2) ah = gear 10 (rf) all other codes are reserved table 52 slimbus clock reference control
WM5102 production data w pd, may 2013, rev 4.0 140 output signal path the WM5102 provides four stereo and one mono analogue output signal paths. these outputs comprise ground-referenced headphone drivers, a differ ential earpiece driver, differential speaker drivers and a digital output interface suitable for exte rnal speaker drivers. t he output signal paths are summarised in table 53. signal path descriptions output pins out1l, out1r ground-referenced headphone output hpout1l, hpout1r out2l, out2r ground-referenced headphone output hpout2l, hpout2r out3 differential (btl) earpiece output epoutp, epoutn out4l, out4r differential speaker output spkoutln, spkoutlp, spkoutrp, spkoutrn out5l, out5r digital speaker (pdm) output spkdat1, spkclk1 table 53 output signal path summary the analogue output paths incorporate high performance 24-bit sigma-delta dacs. under default conditions, the headphone drivers prov ide a stereo, single-ended output. a mono mode is also available on each headphone out put pair, providing a different ial (btl) configuration. the ground-referenced headphone output paths incorporate a common mode feedback path for rejection of system-related noise. these outputs suppor t direct connection to headphone loads, with no requirement for ac coupling capacitors. the earpiece path provides a diffe rential (btl) output, suitable for a typical earpiece load. the differential configuration offers bu ilt-in common mode noise rejection. the speaker output paths are configured to drive a stereo pair of differential (btl) outputs. the class d design offers high efficiency at la rge signal levels. with a suitable choice of external speaker, the class d output can drive loudspeakers directly , without any additional filter components. the digital output path provides a stereo pulse density modulation (pdm) output interface, for connection to exter nal audio devices. digital volume control is available on all out puts (analogue and digital), with programmable ramp control for smooth, glitch-free operation. any of the output signal paths may be selected as input to the acoustic echo cancellation (aec) loopback path. the WM5102 output signal paths are illustrated in figure 52.
production data WM5102 w pd, may 2013, rev 4.0 141 out5_osr 0 = normal mode 1 = high performance dac dac spkoutlp spkoutln spkoutrp spkoutrn out4l_ena out4r_ena hpout2l hpout1l spk1_mute_endian spk1_mute_seq spk1l_mute spk1r_mute pdm output driver spkclk spkdat spk1_fmt out5l_ena out5r_ena mute sequence ep_ena hp2l_ena hp1l_ena hp1r_ena hp2r_ena out1_mono out2_mono dac dac dac dac dac hpout1r hpout2r epoutp epoutn aec loopback input digital core out5l_vol [6:0] out5r_vol [6:0] out5l output out5r output out4l_vol [6:0] out4r_vol [6:0] out4l output out4r output out3_vol [6:0] out3l output out2l_vol [6:0] out2r_vol [6:0] out2l output out2r output out1l_vol [6:0] out1r_vol [6:0] out1l output out1r output aec_loopback_ena aec_loopback_src [1:0] out4_osr 0 = normal mode 1 = high performance mode figure 52 output signal paths
WM5102 production data w pd, may 2013, rev 4.0 142 output signal path enable the output signal paths are enabled usi ng the register bits described in table 54. the respective bit(s) must be enabled for analogue or digital output on the respective output path(s). the supply rails for outputs (out1, out2 and out3) are generated using an integrated dual-mode charge pump, cp1. the charge pump is enabled automatically by the WM5102 when required by the output drivers. see the ?charge pumps, regulators and voltage reference? section for further details. the WM5102 schedules a pop-suppressed control s equence to enable or disable the out1, out2 and out3 signal paths. this is automatically managed in response to setting the respective hpnx_ena or ep_ena register bits. see ?c ontrol write sequencer? for further details. the system clock, sysclk, must be confi gured and enabled before any audio path is enabled. the asyncclk may also be required, depending on the pat h configuration. see ?clocking and sample rates? for details of the system clocks. the WM5102 performs automatic checks to confir m that the sysclk frequency is high enough to support the output signal paths and associated dacs . if an attempt is made to enable an output signal path, and there are insufficient sysclk cycles to support it, then the attempt will be unsuccessful. (note that any signal paths that are already acti ve will not be affected under these circumstances.) the underclocked error condition c an be monitored using the gpio and/or interrupt functions. see ?general purpose input / output? and ?interrupts? for further details. the status bits in register r1025 and r1030 indicate the status of each of the output signal paths. if an underclocked error condition occu rs, then these bits provide readba ck of which signal path(s) have been successfully enabled. register address bit label default description r1024 (0400h) output enables 1 9 out5l_ena 0 output path 5 (left) enable 0 = disabled 1 = enabled 8 out5r_ena 0 output path 5 (right) enable 0 = disabled 1 = enabled 7 out4l_ena 0 output path 4 (left) enable 0 = disabled 1 = enabled 6 out4r_ena 0 output path 4 (right) enable 0 = disabled 1 = enabled 5 ep_ena 0 output path 3 enable 0 = disabled 1 = enabled 3 hp2l_ena 0 output path 2 (left) enable 0 = disabled 1 = enabled 2 hp2r_ena 0 output path 2 (right) enable 0 = disabled 1 = enabled 1 hp1l_ena 0 output path 1 (left) enable 0 = disabled 1 = enabled 0 hp1r_ena 0 output path 1 (right) enable 0 = disabled 1 = enabled r1025 (0401h) output 9 out5l_ena_st s 0 output path 5 (left) enable status 0 = disabled 1 = enabled
production data WM5102 w pd, may 2013, rev 4.0 143 register address bit label default description status 1 8 out5r_ena_st s 0 output path 5 (right) enable status 0 = disabled 1 = enabled 7 out4l_ena_st s 0 output path 4 (left) enable status 0 = disabled 1 = enabled 6 out4r_ena_st s 0 output path 4 (right) enable status 0 = disabled 1 = enabled r1030 (0406h) raw output status 1 5 out3_ena_sts 0 output path 3 enable status 0 = disabled 1 = enabled 3 out2l_ena_st s 0 output path 2 (left) enable status 0 = disabled 1 = enabled 2 out2r_ena_st s 0 output path 2 (right) enable status 0 = disabled 1 = enabled 1 out1l_ena_st s 0 output path 1 (left) enable status 0 = disabled 1 = enabled 0 out1r_ena_st s 0 output path 1 (right) enable status 0 = disabled 1 = enabled table 54 output signal path enable output signal path sample rate control the output signal paths are derived from the respecti ve output mixers within the WM5102 digital core. the sample rate for the output signal paths is conf igured using the out_rate register - see table 20 within the ?digital core? section. note that sample rate conversion is required when routing the output signal paths to any signal chain that is asynchronous and/or configured for a different sample rate.
WM5102 production data w pd, may 2013, rev 4.0 144 output signal path control a high performance mode can be selected on the s peaker output signal paths (out4 and out5) by setting the _osr bits for the re spective paths. when the _osr bi t is set, the audio performance is improved, but power consumption is also increased. the spkclk frequency of the pdm output path (out5) is controlled by the out5_osr register, as described in table 55. when the out5_osr bit is set, the audio performance is improved, but power consumption is also increased. note that the spkclk frequencies noted in table 55 assume that the sysclk frequency is a multiple of 6.144mhz (sysclk_frac=0). if the sysclk frequency is a multiple of 5.6448mhz (sysclk_frac=1), then the spkclk frequencies will be scaled accordingly. condition spkclk frequency out5_osr = 0 3.072mhz out5_osr = 1 6.144mhz table 55 spkclk frequency register address bit label default description r1064 (0428h) output path config 4l 13 out4_osr 0 output path 4 oversample rate 0 = normal mode 1 = high performance mode r1072 (0430h) output path config 5l 13 out5_osr 0 output path 5 oversample rate 0 = normal mode 1 = high performance mode table 56 output signal path control
production data WM5102 w pd, may 2013, rev 4.0 145 output signal path digital volume control a digital volume control is provided on each of t he output signal paths, providing -64db to +31.5db gain control in 0.5db steps. an independent mute cont rol is also provided for each output signal path. whenever the gain or mute setting is changed, the signal path gain is ramped up or down to the new settings at a programmable rate. for increasing gai n (or un-mute), the rate is controlled by the out_vi_ramp register. for decreasing gain (or mute ), the rate is controlled by the out_vd_ramp register. note that the out_vi_ramp and out_vd_ramp registers should not be changed while a volume ramp is in progress. the out_vu bits control the loading of the output signal path digital volume and mute controls. when out_vu is set to 0, the digital volume and mute settings will be loaded into the respective control register, but will not actually change the signal path gain. the digital volume and mute settings on all of the output signal paths are updated when a 1 is wr itten to out_vu. this makes it possible to update the gain of multiple signal paths simultaneously. for correct gain ramp behaviour, the out_vu bits should not be written during the 0.28ms after any of the output path enable bits (see table 54) hav e been asserted. it is recommended that the output path mute bit be set when the respective output driver is enabled; the signal path can then be un- muted after the 0.28ms has elapsed. note that, although the digital volume control regi sters provide 0.5db steps, the internal circuits provide signal gain adjustment in 0.125db steps. this allows a very high degree of gain control, and smooth volume ramping under all operating conditions. the digital volume control register fiel ds are described in table 57 and table 58. register address bit label default description r1033 (0409h) output volume ramp 6:4 out_vd_ramp [2:0] 010 output volume decreasing ramp rate (seconds/6db) 000 = 0ms 001 = 0.5ms 010 = 1ms 011 = 2ms 100 = 4ms 101 = 8ms 110 = 15ms 111 = 30ms this register should not be changed while a volume ramp is in progress. 2:0 out_vi_ramp [2:0] 010 output volume increasing ramp rate (seconds/6db) 000 = 0ms 001 = 0.5ms 010 = 1ms 011 = 2ms 100 = 4ms 101 = 8ms 110 = 15ms 111 = 30ms this register should not be changed while a volume ramp is in progress. r1041 (0411h) dac digital volume 1l 9 out_vu output signal paths volume update writing a 1 to this bit will cause the output signal paths volume and mute settings to be updated simultaneously 8 out1l_mute 1 output path 1 (left) digital mute 0 = un-mute 1 = mute
WM5102 production data w pd, may 2013, rev 4.0 146 register address bit label default description 7:0 out1l_vol [7:0] 80h output path 1 (left) digital volume -64db to +31.5db in 0.5db steps 00h = -64db 01h = -63.5db ? (0.5db steps) 80h = 0db ? (0.5db steps) bfh = +31.5db c0h to ffh = reserved (see table 58 for volume range) r1045 (0415h) dac digital volume 1r 9 out_vu output signal paths volume update writing a 1 to this bit will cause the output signal paths volume and mute settings to be updated simultaneously 8 out1r_mute 1 output path 1 (right) digital mute 0 = un-mute 1 = mute 7:0 out1r_vol [7:0] 80h output path 1 (right) digital volume -64db to +31.5db in 0.5db steps 00h = -64db 01h = -63.5db ? (0.5db steps) 80h = 0db ? (0.5db steps) bfh = +31.5db c0h to ffh = reserved (see table 58 for volume range) r1049 (0419h) dac digital volume 2l 9 out_vu output signal paths volume update writing a 1 to this bit will cause the output signal paths volume and mute settings to be updated simultaneously 8 out2l_mute 1 output path 2 (left) digital mute 0 = un-mute 1 = mute 7:0 out2l_vol [7:0] 80h output path 2 (left) digital volume -64db to +31.5db in 0.5db steps 00h = -64db 01h = -63.5db ? (0.5db steps) 80h = 0db ? (0.5db steps) bfh = +31.5db c0h to ffh = reserved (see table 58 for volume range) r1053 (041dh) dac digital volume 2r 9 out_vu output signal paths volume update writing a 1 to this bit will cause the output signal paths volume and mute settings to be updated simultaneously 8 out2r_mute 1 output path 2 (right) digital mute 0 = un-mute 1 = mute
production data WM5102 w pd, may 2013, rev 4.0 147 register address bit label default description 7:0 out2r_vol [7:0] 80h output path 2 (right) digital volume -64db to +31.5db in 0.5db steps 00h = -64db 01h = -63.5db ? (0.5db steps) 80h = 0db ? (0.5db steps) bfh = +31.5db c0h to ffh = reserved (see table 58 for volume range) r1057 (0421h) dac digital volume 3l 9 out_vu output signal paths volume update writing a 1 to this bit will cause the output signal paths volume and mute settings to be updated simultaneously 8 out3_mute 1 output path 3 digital mute 0 = un-mute 1 = mute 7:0 out3_vol [7:0] 80h output path 3 digital volume -64db to +31.5db in 0.5db steps 00h = -64db 01h = -63.5db ? (0.5db steps) 80h = 0db ? (0.5db steps) bfh = +31.5db c0h to ffh = reserved (see table 58 for volume range) r1065 (0429h) dac digital volume 4l 9 out_vu output signal paths volume update writing a 1 to this bit will cause the output signal paths volume and mute settings to be updated simultaneously 8 out4l_mute 1 output path 4 (left) digital mute 0 = un-mute 1 = mute 7:0 out4l_vol [7:0] 80h output path 4 (left) digital volume -64db to +31.5db in 0.5db steps 00h = -64db 01h = -63.5db ? (0.5db steps) 80h = 0db ? (0.5db steps) bfh = +31.5db c0h to ffh = reserved (see table 58 for volume range) r1069 (042dh) dac digital volume 4r 9 out_vu output signal paths volume update writing a 1 to this bit will cause the output signal paths volume and mute settings to be updated simultaneously 8 out4r_mute 1 output path 4 (right) digital mute 0 = un-mute 1 = mute
WM5102 production data w pd, may 2013, rev 4.0 148 register address bit label default description 7:0 out4r_vol [7:0] 80h output path 4 (right) digital volume -64db to +31.5db in 0.5db steps 00h = -64db 01h = -63.5db ? (0.5db steps) 80h = 0db ? (0.5db steps) bfh = +31.5db c0h to ffh = reserved (see table 58 for volume range) r1073 (0431h) dac digital volume 5l 9 out_vu output signal paths volume update writing a 1 to this bit will cause the output signal paths volume and mute settings to be updated simultaneously 8 out5l_mute 1 output path 5 (left) digital mute 0 = un-mute 1 = mute 7:0 out5l_vol [7:0] 80h output path 5 (left) digital volume -64db to +31.5db in 0.5db steps 00h = -64db 01h = -63.5db ? (0.5db steps) 80h = 0db ? (0.5db steps) bfh = +31.5db c0h to ffh = reserved (see table 58 for volume range) r1077 (0435h) dac digital volume 5r 9 out_vu output signal paths volume update writing a 1 to this bit will cause the output signal paths volume and mute settings to be updated simultaneously 8 out5r_mute 1 output path 5 (right) digital mute 0 = un-mute 1 = mute 7:0 out5r_vol [7:0] 80h output path 5 (right) digital volume -64db to +31.5db in 0.5db steps 00h = -64db 01h = -63.5db ? (0.5db steps) 80h = 0db ? (0.5db steps) bfh = +31.5db c0h to ffh = reserved (see table 58 for volume range) table 57 output signal path digital volume control
production data WM5102 w pd, may 2013, rev 4.0 149 output volume register volume (db) output volume register volume (db) output volume register volume (db) output volume register volume (db) 00h -64.0 40h -32.0 80h 0.0 c0h reserved 01h -63.5 41h -31.5 81h 0.5 c1h reserved 02h -63.0 42h -31.0 82h 1.0 c2h reserved 03h -62.5 43h -30.5 83h 1.5 c3h reserved 04h -62.0 44h -30.0 84h 2.0 c4h reserved 05h -61.5 45h -29.5 85h 2.5 c5h reserved 06h -61.0 46h -29.0 86h 3.0 c6h reserved 07h -60.5 47h -28.5 87h 3.5 c7h reserved 08h -60.0 48h -28.0 88h 4.0 c8h reserved 09h -59.5 49h -27.5 89h 4.5 c9h reserved 0ah -59.0 4ah -27.0 8ah 5.0 cah reserved 0bh -58.5 4bh -26.5 8bh 5.5 cbh reserved 0ch -58.0 4ch -26.0 8ch 6.0 cch reserved 0dh -57.5 4dh -25.5 8dh 6.5 cdh reserved 0eh -57.0 4eh -25.0 8eh 7.0 ceh reserved 0fh -56.5 4fh -24.5 8fh 7.5 cfh reserved 10h -56.0 50h -24.0 90h 8.0 d0h reserved 11h -55.5 51h -23.5 91h 8.5 d1h reserved 12h -55.0 52h -23.0 92h 9.0 d2h reserved 13h -54.5 53h -22.5 93h 9.5 d3h reserved 14h -54.0 54h -22.0 94h 10.0 d4h reserved 15h -53.5 55h -21.5 95h 10.5 d5h reserved 16h -53.0 56h -21.0 96h 11.0 d6h reserved 17h -52.5 57h -20.5 97h 11.5 d7h reserved 18h -52.0 58h -20.0 98h 12.0 d8h reserved 19h -51.5 59h -19.5 99h 12.5 d9h reserved 1ah -51.0 5ah -19.0 9ah 13.0 dah reserved 1bh -50.5 5bh -18.5 9bh 13.5 dbh reserved 1ch -50.0 5ch -18.0 9ch 14.0 dch reserved 1dh -49.5 5dh -17.5 9dh 14.5 ddh reserved 1eh -49.0 5eh -17.0 9eh 15.0 deh reserved 1fh -48.5 5fh -16.5 9fh 15.5 dfh reserved 20h -48.0 60h -16.0 a0h 16.0 e0h reserved 21h -47.5 61h -15.5 a1h 16.5 e1h reserved 22h -47.0 62h -15.0 a2h 17.0 e2h reserved 23h -46.5 63h -14.5 a3h 17.5 e3h reserved 24h -46.0 64h -14.0 a4h 18.0 e4h reserved 25h -45.5 65h -13.5 a5h 18.5 e5h reserved 26h -45.0 66h -13.0 a6h 19.0 e6h reserved 27h -44.5 67h -12.5 a7h 19.5 e7h reserved 28h -44.0 68h -12.0 a8h 20.0 e8h reserved 29h -43.5 69h -11.5 a9h 20.5 e9h reserved 2ah -43.0 6ah -11.0 aah 21.0 eah reserved 2bh -42.5 6bh -10.5 abh 21.5 ebh reserved 2ch -42.0 6ch -10.0 ach 22.0 ech reserved 2dh -41.5 6dh -9.5 adh 22.5 edh reserved 2eh -41.0 6eh -9.0 aeh 23.0 eeh reserved 2fh -40.5 6fh -8.5 afh 23.5 efh reserved 30h -40.0 70h -8.0 b0h 24.0 f0h reserved 31h -39.5 71h -7.5 b1h 24.5 f1h reserved 32h -39.0 72h -7.0 b2h 25.0 f2h reserved 33h -38.5 73h -6.5 b3h 25.5 f3h reserved 34h -38.0 74h -6.0 b4h 26.0 f4h reserved 35h -37.5 75h -5.5 b5h 26.5 f5h reserved 36h -37.0 76h -5.0 b6h 27.0 f6h reserved 37h -36.5 77h -4.5 b7h 27.5 f7h reserved 38h -36.0 78h -4.0 b8h 28.0 f8h reserved 39h -35.5 79h -3.5 b9h 28.5 f9h reserved 3ah -35.0 7ah -3.0 bah 29.0 fah reserved 3bh -34.5 7bh -2.5 bbh 29.5 fbh reserved 3ch -34.0 7ch -2.0 bch 30.0 fch reserved 3dh -33.5 7dh -1.5 bdh 30.5 fdh reserved 3eh -33.0 7eh -1.0 beh 31.0 feh reserved 3fh -32.5 7fh -0.5 bfh 31.5 ffh reserved table 58 output signal path digital volume range
WM5102 production data w pd, may 2013, rev 4.0 150 output signal path digital volume limit a digital limit control is provided on each of t he output signal paths. any signal which exceeds the applicable limit will be clipped at that level. the lim it control is implemented in the digital domain, before the output path dacs. for typical applications, a limit of 0dbfs is recommended for the analogue output paths (out1, out2, out3 and out4). the digital speaker output (out 5) can handle signal levels up to +3dbfs; a maximum setting of +3dbfs is recommended for this output path. caution is advised when selecting other limits, as the output signal may clip in the digital and/or analogue stages of the respective signal path(s). the digital limit register fields are described in table 59 and table 60. register address bit label default description r1042 (0412h dac volume limit 1l 7:0 out1l_vol_lim [7:0] 81h output path 1 (left) digital limit -6dbfs to +6dbfs in 0.5db steps 00h to 73h = reserved 74h = -6.0dbfs 75h = -5.5dbfs ? (0.5db steps) 80h = 0.0dbfs ? (0.5db steps) 8bh = +5.5dbfs 8ch = +6.0dbfs 8dh to ffh = reserved (see table 60 for limit range) r1046 (0416h dac volume limit 1r 7:0 out1r_vol_li m [7:0] 81h output path 1 (right) digital limit -6dbfs to +6dbfs in 0.5db steps 00h to 73h = reserved 74h = -6.0dbfs 75h = -5.5dbfs ? (0.5db steps) 80h = 0.0dbfs ? (0.5db steps) 8bh = +5.5dbfs 8ch = +6.0dbfs 8dh to ffh = reserved (see table 60 for limit range) r1050 (041ah dac volume limit 2l 7:0 out2l_vol_lim [7:0] 81h output path 2 (left) digital limit -6dbfs to +6dbfs in 0.5db steps 00h to 73h = reserved 74h = -6.0dbfs 75h = -5.5dbfs ? (0.5db steps) 80h = 0.0dbfs ? (0.5db steps) 8bh = +5.5dbfs 8ch = +6.0dbfs 8dh to ffh = reserved (see table 60 for limit range)
production data WM5102 w pd, may 2013, rev 4.0 151 register address bit label default description r1054 (041eh dac volume limit 2r 7:0 out2r_vol_li m [7:0] 81h output path 2 (right) digital limit -6dbfs to +6dbfs in 0.5db steps 00h to 73h = reserved 74h = -6.0dbfs 75h = -5.5dbfs ? (0.5db steps) 80h = 0.0dbfs ? (0.5db steps) 8bh = +5.5dbfs 8ch = +6.0dbfs 8dh to ffh = reserved (see table 60 for limit range) r1058 (0422h dac volume limit 3l 7:0 out3_vol_lim [7:0] 81h output path 3 digital limit -6dbfs to +6dbfs in 0.5db steps 00h to 73h = reserved 74h = -6.0dbfs 75h = -5.5dbfs ? (0.5db steps) 80h = 0.0dbfs ? (0.5db steps) 8bh = +5.5dbfs 8ch = +6.0dbfs 8dh to ffh = reserved (see table 60 for limit range) r1066 (042ah out volume 4l 7:0 out4l_vol_lim [7:0] 81h output path 4 (left) digital limit -6dbfs to +6dbfs in 0.5db steps 00h to 73h = reserved 74h = -6.0dbfs 75h = -5.5dbfs ? (0.5db steps) 80h = 0.0dbfs ? (0.5db steps) 8bh = +5.5dbfs 8ch = +6.0dbfs 8dh to ffh = reserved (see table 60 for limit range) r1070 (042eh out volume 4r 7:0 out4r_vol_li m [7:0] 81h output path 4 (right) digital limit -6dbfs to +6dbfs in 0.5db steps 00h to 73h = reserved 74h = -6.0dbfs 75h = -5.5dbfs ? (0.5db steps) 80h = 0.0dbfs ? (0.5db steps) 8bh = +5.5dbfs 8ch = +6.0dbfs 8dh to ffh = reserved (see table 60 for limit range)
WM5102 production data w pd, may 2013, rev 4.0 152 register address bit label default description r1074 (0432h dac volume limit 5l 7:0 out5l_vol_lim [7:0] 81h output path 5 (left) digital limit -6dbfs to +6dbfs in 0.5db steps 00h to 73h = reserved 74h = -6.0dbfs 75h = -5.5dbfs ? (0.5db steps) 80h = 0.0dbfs ? (0.5db steps) 8bh = +5.5dbfs 8ch = +6.0dbfs 8dh to ffh = reserved (see table 60 for limit range) r1078 (0436h dac volume limit 5r 7:0 out5r_vol_li m [7:0] 81h output path 5 (right) digital limit -6dbfs to +6dbfs in 0.5db steps 00h to 73h = reserved 74h = -6.0dbfs 75h = -5.5dbfs ? (0.5db steps) 80h = 0.0dbfs ? (0.5db steps) 8bh = +5.5dbfs 8ch = +6.0dbfs 8dh to ffh = reserved (see table 60 for limit range) table 59 output signal path digital limit control
production data WM5102 w pd, may 2013, rev 4.0 153 outnl_vol_lim[7:0], outnr_vol_lim[7:0] limit (dbfs) 00h to 73h reserved 74h -6.0 75h -5.5 76h -5.0 77h -4.5 78h -4.0 79h -3.5 7ah -3.0 7bh -2.5 7ch -2.0 7dh -1.5 7eh -1.0 7fh -0.5 80h 0.0 81h +0.5 82h +1.0 83h +1.5 84h +2.0 85h +2.5 86h +3.0 87h +3.5 88h +4.0 89h +4.5 8ah +5.0 8bh +5.5 8ch +6.0 8dh to ffh reserved table 60 output signal path digital limit range
WM5102 production data w pd, may 2013, rev 4.0 154 output signal path noise gate control the WM5102 provides a digital noise gate function for each of the out put signal paths. the noise gate ensures best noise performance w hen the signal path is idle. when the noise gate is enabled, and the applicable signal level is below the noise gate threshol d, then the noise gate is activated, causing the signal path to be muted. the noise gate function is enabled using the ngat e_ena register, as described in table 61. for each output path, the noise gate may be associat ed with one or more of the signal path threshold detection functions using the _ngate_src register fields. w hen more than one signal threshold is selected, then the output path noise gate is only activa ted (ie. muted) when all of the respective signal thresholds are satisfied. for example, if the out1l noise gate is asso ciated with the out1l and out1r signal paths, then the out1l signal path will only be muted if both the out1l and out1r signal levels are below the respective thresholds. the noise gate threshold (the signal level below wh ich the noise gate is activated) is set using ngate_thr. note that, for each output path, the noi se gate threshold represents the signal level at the respective output pin(s) - the threshold is therefore independent of the digital volume and pga gain settings. note that, although there is only one noise gate th reshold level (ngate_thr), each of the output path noise gates may be activated independently, accord ing to the respective signal content and the associated threshold configuration(s). to prevent erroneous triggering, a ti me delay is applied before the gate is activated; the noise gate is only activated (ie. muted) when the output levels ar e below the applicable signal level threshold(s) for longer than the noise gate ?hold time?. the ?hold time? is set using the ngate_hold register. when the noise gate is activated, the WM5102 gradually attenuates the respective signal path at the rate set by the out_vd_ramp register (see tabl e 57). when the noise gate is de-activated, the output volume increases at the rate set by the out_vi_ramp register. register address bit label default description r1043 (0413h) noise gate select 1l 11:0 out1l_ngate_ src [11:0] 001h output signal path noise gate source enables one of more signal paths as inputs to the respective noise gate. if more than one signal path is enabled as an input, the noise gate is only activated (ie. muted) when all of the respective signal thresholds are satisfied. [11] = reserved [10] = reserved [9] = out5r [8] = out5l [7] = out4r [6] = out4l [5] = reserved [4] = out3 [3] = out2r [2] = out2l [1] = out1r [0] = out1l each bit is coded as: 0 = disabled r1047 (0417h) noise gate select 1r 11:0 out1r_ngate_ src [11:0] 002h r1051 (041bh) noise gate select 2l 11:0 out2l_ngate_ src [11:0] 004h r1055 (041fh) noise gate select 2r 11:0 out2r_ngate_ src [11:0] 008h r1059 (0423h) noise gate select 3l 11:0 out3_ngate_s rc [11:0] 010h
production data WM5102 w pd, may 2013, rev 4.0 155 register address bit label default description r1067 (042bh) noise gate select 4l 11:0 out4l_ngate_ src [11:0] 040h 1 = enabled r1071 (042fh) noise gate select 4r 11:0 out4r_ngate_ src [11:0] 080h r1075 (0433h) noise gate select 5l 11:0 out5l_ngate_ src [11:0] 100h r1079 (0437h) noise gate select 5r 11:0 out5r_ngate_ src [11:0] 200h r1112 (0458h) noise gate control 5:4 ngate_hold [1:0] 00 output signal path noise gate hold time (delay before noise gate is activated) 00 = 30ms 01 = 120ms 10 = 250ms 11 = 500ms 3:1 ngate_thr [2:0] 000 output signal path noise gate threshold 000 = -60db 001 = -66db 010 = -72db 011 = -78db 100 = -84db 101 = -90db 110 = -96db 111 = -102db 0 ngate_ena 1 output signal path noise gate enable 0 = disabled 1 = enabled table 61 output signal path noise gate control
WM5102 production data w pd, may 2013, rev 4.0 156 output signal path aec loopback the WM5102 incorporates loopback signal path, which is ideally suited as a reference for acoustic echo cancellation (aec) processing. any of the output signal paths may be selected as the aec loopback source. when configured with suitable dsp firmware, t he WM5102 can provide an integrated aec capability. the aec loopback feature also enables convenient hook-up to an external device for implementing the required signal processing algorithms. the aec loopback source is connected after the respecti ve digital volume controls, as illustrated in figure 52. a digital gain control is incorporated in the aec loopback path, which is automatically set according to the pga gain of the selected output path, where applicable. when out1n, out2n or out3 is selected as the aec loopback source, the loopback gain matches the corresponding pga gain, ensuring that the loopback signal level will ex actly match the selected output, regardless of the digital or analogue gain settings. the aec loopback signal can be selected as input to any of the digital mixers within the WM5102 digital core. the sample rate for the aec loopback pat h is configured using t he out_rate register - see table 20 within the ?digital core? section. the aec loopback function is enabled using the aec _loopback_ena register. the source signal for the transmit path aec function is se lected using the aec_loopback_src register. the WM5102 performs automatic checks to confir m that the sysclk frequency is high enough to support the aec loopback function. if an attempt is made to enable this function, and there are insufficient sysclk cycles to support it, then the attempt will be unsuccessful. (note that any signal paths that are already active will not be affected under these circumstances.) the underclocked error condition c an be monitored using the gpio and/or interrupt functions. see ?general purpose input / output? and ?interrupts? for further details. the aec_ena_sts register indicates the status of the aec loopback function. if an underclocked error condition occurs, then this bit can provide indication of w hether the aec loopback function has been successfully enabled. register address bit label default description r1104 (0450h) dac aec control 1 5:2 aec_loopbac k_src [3:0] 0000 input source for tx aec function 0000 = out1l 0001 = out1r 0010 = out2l 0011 = out2r 0100 = out3 0110 = out4l 0111 = out4r 1000 = out5l 1001 = out5r all other codes are reserved 1 aec_ena_sts 0 transmit (tx) path aec control status 0 = disabled 1 = enabled 0 aec_loopbac k_ena 0 transmit (tx) path aec control 0 = disabled 1 = enabled table 62 output signal path aec loopback control
production data WM5102 w pd, may 2013, rev 4.0 157 headphone/earpiece outputs and mono mode the headphone drivers can provide a mono differential (btl) output; this is ideal for driving an earpiece or hearing aid coil. the mono differentia l (btl) configuration is selected using the outn_mono register bits. when the outn_mono bi t is set, then the respective right channel output is an inverted copy of the left channel output signal; this creates a differential output between the respective outnl and outnr pins. in mono configuration, the effective gai n of the signal path is increased by 6db. the mono (btl) signal paths are illustrated in figure 52. the out1l and out1r output signal paths are associated with the analogue outputs hpout1l and hpout1r respectively. the out2l and out2r output signal paths are associated with the analogue outputs hpout2l and hpout2r respectively. the out3 output signal path is associated with the analogue outputs epoutp and epoutn. register address bit label default description r1040 (0410h) output path config 1l 12 out1_mono 0 output path 1 mono mode (configures hpout1l and hpout1r as a mono differential output.) 0 = disabled 1 = enabled the gain of the signal path is increased by 6db in differential (mono) mode. r1048 (0418h) output path config 2l 12 out2_mono 0 output path 2 mono mode (configures hpout2l and hpout2r as a mono differential output.) 0 = disabled 1 = enabled the gain of the signal path is increased by 6db in differential (mono) mode. table 63 headphone driver mono mode control the headphone driver outputs hpout1l, hpout1r, hpout2l and hpout2r are suitable for direct connection to external headphones and ear pieces. the outputs are ground-referenced, eliminating any requirement for ac coupling capacitors. the headphone outputs incorporate a common mode, or ground loop, feedback path which provides rejection of system-related ground noise. the feedback pins must be connected to ground for normal operation of the headphone outputs. note that the feedback pins should be connected to gnd close to the respective headphone jack, as illustrated in figure 53. in mono (differential) mode, the feedback pin(s) should be connected to the ground plane that is physically closest to the earpiece output pcb tracks. the ground feedback path for hpout1l and hpout1 r is provided via the hpout1fb1 or hpout1fb2 pins; the applicable c onnection must be selected using the accdet_src register, as described in table 64. the ground feedback path for hpout2l and hpout2r is provided via the hpout2fb pin. no register configuration is requi red for the hpout2fb connection.
WM5102 production data w pd, may 2013, rev 4.0 158 register address bit label default description r659 (0293h) accessory detect mode 1 13 accdet_src 0 accessory detect / headphone feedback pin select 0 = accessory detect on micdet1, headphone ground feedback on hpout1fb1 1 = accessory detect on micdet2, headphone ground feedback on hpout1fb2 table 64 headphone output (hpout1) ground feedback control the earpiece driver outputs epout p and epoutn are suitable for dire ct connection to an earpiece. the output configuration is differential (btl), drivi ng both ends of the external load directly - note that there is no associated ground connection. the headphone and earpiece connections ar e illustrated in figure 53. figure 53 headphone and earpiece connection
production data WM5102 w pd, may 2013, rev 4.0 159 speaker outputs (analogue) the speaker driver outputs spkoutlp, spko utln, spkoutlp and spkoutln provide two differential (btl) outputs suitable for direct connecti on to external loudspeakers. the integrated class d speaker driver prov ides high efficiency at large signal levels. the speaker driver signal paths in corporate a boost function which shi fts the signal levels between the avdd and spkvdd voltage domains. the boost is pre-configured (+12db) for the recommended avdd and spkvdd operating voltages (see ?r ecommended operating conditions?). ultra-low leakage and high psrr allow the speaker supply spkvdd to be connected directly to a lithium battery. note that spkvddl powers the left speaker driver, and spkvddr powers the right speaker driver; it is assumed that spkvddl = spkvddr = spkvdd. note that sysclk must be present and enabled when using the class d speaker output; see ?clocking and sample rates? for details of sysc lk and the associated register control fields. the out4l and out4r output signal paths are associated with the analogue outputs spkoutlp, spkoutln, spkoutlp and spkoutln. the class d speaker output is a pulse width modulat ed signal, and requires external filtering in order to recreate the audio signal. with a suitable choice of external speakers, the speakers themselves can provide the necessary filtering. see ?applications information? for further information on class d speaker connections. the external speaker connection is illustrated in figure 54, assuming suitable speakers are chosen to provide the pwm filtering. figure 54 speaker connection speaker outputs (digital pdm) the WM5102 supports a two-channel pulse density modul ation (pdm) digital speaker interface; the pdm outputs are associated with the out5l and out5r output signal paths. the pdm digital speaker interface is illustrated in figure 55. the out5l and out5r output signal paths are in terleaved on the spkdat output pin, and clocked using spkclk. note that the pdm interface supports two differ ent operating modes; these are selected using the spk1_fmt register bit. see ?signal timing requirements? for deta iled timing information in both modes. when spk1_fmt = 0 (mode b), then the left pdm c hannel is valid during the low phase of spkclk; the right pdm channel is valid during the high phase of spkclk. when spk1_fmt = 1 (mode a), then the left pdm channel is valid at the rising edge of spkclk; the right pdm channel is valid at the falling edge of spkclk.
WM5102 production data w pd, may 2013, rev 4.0 160 figure 55 digital speaker (pdm) interface timing clocking for the pdm interface is derived from sysc lk. note that the sysclk_ena register must also be set. see ?clocking and sample rates? for fu rther details of the system clocks and control registers. when the out5l or out5r output signal path is enabl ed, the pdm interface clock signal is output on the spkclk1 pin. the output signal paths support normal and high per formance operating modes, as described in the ?output signal path? section. the spkclk n frequency is set according to the operating mode of the relevant output path, as described in table 65. out5_osr description spkclk1 frequency 0 normal mode 3.072mhz 1 high performance mode 6.144mhz table 65 spkclk1 frequency the pdm output channels can be independently mut ed. when muted, the default output on each channel is a dsd-compliant silent stream (0110_1001b). the mute output code can be programmed to other values if required, using the spk1_mute_ seq register field. the mute output code can be transmitted msb-first or lsb-fi rst; this is selectable using the spk1_mute_endian register. note that the pdm mute function is not a soft-mu te; the audio output is interrupted immediately when the pdm mute is asserted. it is recommended to us e the output signal path mute function before applying the pdm mute. see table 57 for details of the out5l_mute and out5r_mute registers. the pdm output interface registers are described in table 66.
production data WM5102 w pd, may 2013, rev 4.0 161 register address bit label default description r1168 (0490h) pdm spk1 ctrl 1 13 spk1r_mute 0 pdm speaker output 1 (right) mute 0 = audio output (out5r) 1 = mute sequence output 12 spk1l_mute 0 pdm speaker output 1 (left) mute 0 = audio output (out5l) 1 = mute sequence output 8 spk1_mute_en dian 0 pdm speaker output 1 mute sequence control 0 = mute sequence is lsb first 1 = mute sequence output is msb first 7:0 spk1_mute_se q [7:0] 69h pdm speaker output 1 mute sequence defines the 8-bit code that is output on spkdat1 (left) or spkdat1 (right) when muted. r1169 (0491h) pdm spk1 ctrl 2 0 spk1_fmt 0 pdm speaker output 1 timing format 0 = mode b (pdm data is valid during the high/low phase of spkclk1) 1 = mode a (pdm data is valid at the rising/falling edges of spkclk1) table 66 digital speaker (pdm) output control the digital speaker (pdm) outputs spkdat and spkc lk are intended for direct connection to a compatible external speaker driver. a typica l configuration is illustrated in figure 56. figure 56 digital speaker (pdm) connection
WM5102 production data w pd, may 2013, rev 4.0 162 external accessory detection the WM5102 provides external accessory detecti on functions which can sense the presence and impedance of external components. this can be used to detect the insertion or removal of an external headphone or headset, and to provide an indi cation of key/button push events. jack insertion is detected using the jackdet pin, wh ich must be connected to a switch contact within the jack socket. an interrupt event is generated whenev er a jack insertion or jack removal event is detected. the jack detect function can also be used to trigger a wake-up transition (ie. exit from sleep mode) or to trigger the control write sequencer. suppression of pops and clicks caused by jack insert ion or removal is provided using the micdet clamp function. this function can also be used to trigger interrupt events, a wake-up transition (ie. exit from sleep mode) or to tr igger the control write sequencer. microphones, push-buttons and other accessories c an be detected via the micdet1 or micdet2 pins. the presence of a microphone, and the status of a hookswitch can be detected. this feature can also be used to detect push-button operation. headphone impedance can be detected via the hpdetl and hpdetr pins; this can be used to set different gain levels or other configuration setti ngs according to the type of load connected. for example, different settings may be app licable to headphone or line output loads. the micvdd power domain must be enabled when usi ng the accessory detection functions. this power domain is provided using an internal charge pump (cp2) and ldo regulator (ldo2). see ?charge pumps, regulators and voltage refer ence? for details of these circuits. the internal 32khz clock must be present and enabl ed when using the jack insertion or accessory detection functions; see ?clocking and sample rates? for details of the internal 32khz clock and associated register control fields. jack detect the WM5102 provides support for jack insertion swit ch detection. the jack insertion status can be read using the relevant register status bit. a jack insertion or removal can also be used to trigger an interrupt (irq) event or to trigger the control write sequencer. when the WM5102 is in the low-power sleep mode (s ee ?low power sleep configuration?), the jack detect function can be used as a ?wak e-up? input; a typical use case is where an application is idle in standby mode until a headphone or headset jack is inserted. jack insertion and removal is detected using the jackdet pin. the recommended external connection circuit is illustrated in figure 57. the jack detect feature is enabled using jd1_ena; t he jack insertion status can be read using the jd1_sts register. the jackdet input de-bounce is selected using the jd 1_db register, as described in table 67. note that the de-bounce circuit uses the 32khz clock, which must be enabled whenever input de-bounce functions are required. note that the jack detect signal, jd1, can be used as an input to the micdet clamp function. this provides additional functionalit y relating to jack insertion or jack removal events. an interrupt request (irq) event is generated whenever a jack insertion or jack removal is detected (see ?interrupts?). separate ?mask? bits are pr ovided to enable irq events on the rising and/or falling edge of the jd1 status. the control write sequencer can be triggered by a ja ck insertion or jack removal detection. this is enabled using register bits described in the ?low power sleep configuration? section. the control registers associated with the ja ck detect function are described in table 67.
production data WM5102 w pd, may 2013, rev 4.0 163 register address bit label default description r723 (02d3h) jack detect analogue 0 jd1_ena 0 jackdet enable 0 = disabled 1 = enabled r3413 (0d55h) aod irq raw status 0 jd1_sts 0 jackdet input status 0 = jack not detected 1 = jack is detected (assumes the jackdet pin is pulled ?low? on jack insertion.) r3414 (0d56h) jack detect debounce 0 jd1_db 0 jackdet input de-bounce 0 = disabled 1 = enabled table 67 jack detect control a recommended connection circuit, incl uding headphone output on hpout1 and microphone connections, is shown in figure 57. see ?applications information? for details of recommended external components. figure 57 jack detect and external accessory connections the internal comparator circuit used to detect the jackdet status is illustrated in figure 58. the threshold voltages for the jack detect circuit are not ed in the ?electrical characteristics?. note that separate thresholds are defined for jack insertion and jack removal. figure 58 jack detect comparator
WM5102 production data w pd, may 2013, rev 4.0 164 jack pop suppression (micdet clamp) under typical configuration of a 3.5mm headphone/acce ssory jack connection, there is a risk of pops and clicks arising from jack insertion or remo val. this can occur when the headphone load makes momentary contact with the micbias output when the jack is not fully inserted, as illustrated in figure 59. the WM5102 provides a micdet clamp function to suppress pops and clicks caused by jack insertion or removal. the clamp is activated by a configurable logic functi on derived from external logic inputs. the clamp status can be read using the relevant register status bit. the clamp status can also be used to trigger an interrupt (irq) event or to trigger the control write sequencer. when the WM5102 is in the low-power sleep mode (see ?low power sleep configuration?), the micdet clamp function can be used as a ?wake-up? input; a typical use case is where an application is idle in standby mode until a headphone or headset jack is inserted. the micdet clamp function is controlled by a select able logic condition, derived from the jd1 and/or gp5 signals. the function is enabled and confi gured using the micd_clamp_mode register. the jd1 signal is derived from the jack detect function (see table 67). t he gp5 signal is derived from the gpio5 input pin (see ?g eneral purpose input / output?). when the micdet clamp is active, the micdet1 /hpout1fb2 and hpout1fb1/micdet2 pins are short-circuited to gnd. note that both pins ar e shorted, regardless of the accdet_src register. the configurable logic provides flexibility in sele cting the appropriate condi tions for activating the micdet clamp. the clamp status can be read using the micd_clamp_sts register. the micdet clamp de-bounce is selected using t he micd_clamp_db register, as described in table 68. note that the de-bounc e circuit uses the 32khz clo ck, which must be enabled whenever input de-bounce functions are required. an interrupt request (irq) event is generated whenever the micdet clamp is asserted or de- asserted (see ?interrupts?). separate ?mask? bi ts are provided to enable irq events on the rising and/or falling edge of the micdet clamp status. the control write sequencer can be triggered by the micdet clamp status . this is enabled using register bits described in the ?low power sleep configuration? section. the micdet clamp function is illustrated in figure 59. note that the jack plug is shown partially removed, with the micdet1 pin in contact with the headphone load. hpout1fb1/ micdet2 micdet1/ hpout1fb2 micbiasn c * innrp 2.2k (+/-2%) * note: the jack plug is shown partially removed, with the micdet1 pin in contact with the headphone load. * see note micdet clamp control micd_clamp_mode micd_clamp_sts micd_clamp_db WM5102 * note that the right analogue mic channel is recommended with the external accessory detect function figure 59 micdet clamp circuit
production data WM5102 w pd, may 2013, rev 4.0 165 the control registers associated with the mi cdet clamp function are described in table 68. register address bit label default description r674 (02a2h) micd clamp control 3:0 micd_clamp_m ode [3:0] 0000 micdet clamp mode 0h = disabled 1h = active (micdet1 and micdet2 are shorted to gnd) 2h = reserved 3h = reserved 4h = active when jd1=0 5h = active when jd1=1 6h = active when gp5=0 7h = active when gp5=1 8h = active when jd1=0 or gp5=0 9h = active when jd1=0 or gp5=1 ah = active when jd1=1 or gp5=0 bh = active when jd1=1 or gp5=1 ch = active when jd1=0 and gp5=0 dh = active when jd1=0 and gp5=1 eh = active when jd1=1 and gp5=0 fh = active when jd1=1 and gp5=1 r3413 (0d55h) aod irq raw status 3 micd_clamp_s ts 0 micdet clamp status 0 = clamp not active 1 = clamp active note that the micdet clamp is effective on micdet1 and micdet2, regardless of the accdet_src register bit. r3414 (0d56h) jack detect debounce 3 micd_clamp_d b 0 micdet clamp de-bounce 0 = disabled 1 = enabled table 68 micdet clamp control microphone detect the WM5102 microphone detection circui t measures the impedance of an external load connected to one of the micdet pins. this feature can be us ed to detect the presence of a microphone, and the status of the associated hookswitch. it can also be used to detect push-button status or the connection of other external accessories. the microphone detection circuit m easures the impedance connected to micdet1 or micdet2, and reports whether the measured impedance lies within one of 8 pre-defined levels (including the ?no accessory detected? level). this means it can detect the presence of a typical microphone and up to 6 push-buttons. one of the impedance levels is s pecifically designed to detect a video accessory (typical 75 ? ) load if required. the microphone detection circuit typi cally uses one of the micbias outputs as a reference. the WM5102 will automatically enable the appropriate micb ias when required in order to perform the detection function; this allows the detection func tion to be supported in low-power standby operating conditions. note that the micvdd power domain must be enabled when using the micr ophone detection function. this power domain is provided using an internal charge pump (cp2) and ldo regulator (ldo2). see ?charge pumps, regulators and voltage refe rence? for details of these circuits. to select microphone detection on one of the micdet pins, the accdet_mode register must be set to 00. the accdet_mode register is defined in table 69. the WM5102 can only support one headphone or microphone detection function at any time. when the detection function is not in use, it is recommended to set accdet_mode=00.
WM5102 production data w pd, may 2013, rev 4.0 166 the microphone detection circuit c an be enabled on the micdet1 pin or the micdet2 pin, selected by the accdet_src register. an internal pull-down resistor can be enabled on the selected micdetn pin; this is configured using the micd_pd register bit. note that the pull-down is only effective on one of the micdetn pins, as selected by accdet_src. the microphone detection circui t uses micvdd, micbias1, micbias2 or micbias3 as a reference. the applicable source is configured using the micd_bias_src register. when accdet_mode is set to 00, then micr ophone detection is enabled by setting micd_ena. when microphone detection is enabled, the WM5102 perform s a number of measurements in order to determine the micdet impedance. the measurement proc ess is repeated at a cyclic rate controlled by micd_rate. (the micd_rate register selects the delay between completion of one measurement and the start of the next.) for best accuracy, the measured impedance is only deemed valid after more than one successive measurement has produced the same result. the micd_ dbtime register provides control of the de- bounce period; this can be either 2 measurements or 4 measurements. when the microphone detection result has settled (i e. after the applicable de-bounce period), the WM5102 indicates valid data by setting the micd_ valid bit. the measured impedance is indicated using the micd_lvl and micd_sts register bits, as described in table 69. the micd_valid bit, when set, remains asserted fo r as long as the micr ophone detection function is enabled (ie. while micd_ena = 1). if the det ected impedance changes, then the micd_lvl and micd_sts fields will change, but the micd_valid bi t will remain set, indicating valid data at all times. the microphone detection reports a measurement resu lt in one of the pre-defined impedance levels. each measurement level can be enabled or disabled independently; this provides flexibility according to the required thresholds, and offers a faster measurement time in some applications. the micd_lvl_sel register is described in detail later in this section. note that the impedance levels quoted in the micd_lvl description assume that a microphone (475 ? to 30k ? impedance) is also present on the micdet pin. the limits quoted in the ?electrical characteristics? refer to the combined effect ive impedance on the micdet pin. typical external components are described in the ?applications information? section. the microphone detection function is an input to the in terrupt control circuit and can be used to trigger an interrupt event every time an accessory insert ion, removal or impedance change is detected. see ?interrupts? for further details. the microphone detection function can also generate a gpio output, prov iding an external indication of the microphone detection. this gpio output is pul sed every time an accessory insertion, removal or impedance change is detected. see ?general purpose input / output? to configure a gpio pin for this function. the register fields associated with microphone detect ion (or other accessories) are described in table 69. the external circuit configuration is illustrated in figure 60. register address bit label default description r659 (0293h) accessory detect mode 1 13 accdet_src 0 accessory detect / headphone feedback pin select 0 = accessory detect on micdet1, headphone ground feedback on hpout1fb1 1 = accessory detect on micdet2, headphone ground feedback on hpout1fb2
production data WM5102 w pd, may 2013, rev 4.0 167 register address bit label default description 1:0 accdet_mode [1:0] 00 accessory detect mode select 00 = micdet measurement 01 = hpdetl measurement 10 = hpdetr measurement 11 = micdet measurement note that the micdet function is provided on the micdet1 or micdet2 pins, depending on the accdet_src register bit. r675 (02a3h) mic detect 1 15:12 micd_bias_sta rttime [3:0] 0001 mic detect bias startup delay (if micbias is not enabled already, this field selects the delay time allowed for micbias to startup prior to performing the micdet function.) 0000 = 0ms (continuous) 0001 = 0.25ms 0010 = 0.5ms 0011 = 1ms 0100 = 2ms 0101 = 4ms 0110 = 8ms 0111 = 16ms 1000 = 32ms 1001 = 64ms 1010 = 128ms 1011 = 256ms 1100 to 1111 = 512ms 11:8 micd_rate [3:0] 0001 mic detect rate (selects the delay between successive micdet measurements.) 0000 = 0ms (continuous) 0001 = 0.25ms 0010 = 0.5ms 0011 = 1ms 0100 = 2ms 0101 = 4ms 0110 = 8ms 0111 = 16ms 1000 = 32ms 1001 = 64ms 1010 = 128ms 1011 = 256ms 1100 to 1111 = 512ms 5:4 micd_bias_src [1:0] 00 accessory detect (micdet) reference select 00 = micvdd 01 = micbias1 10 = micbias2 11 = micbias3 1 micd_dbtime 1 mic detect de-bounce 0 = 2 measurements 1 = 4 measurements 0 micd_ena 0 mic detect enable 0 = disabled 1 = enabled
WM5102 production data w pd, may 2013, rev 4.0 168 register address bit label default description r676 (02a4h) mic detect 2 7:0 micd_lvl_sel [7:0] 1001_ 1111 mic detect level select (enables mic/accessory detection in specific impedance ranges) [7] = enable >475 ohm detection [6] = not used - must be set to 0 [5] = not used - must be set to 0 [4] = enable 375 ohm detection [3] = enable 155 ohm detection [2] = enable 73 ohm detection [1] = enable 40 ohm detection [0] = enable 18 ohm detection note that the impedance values quoted assume that a microphone (475ohm- 30kohm) is also present on the micdet pin. r677 (02a5h) mic detect 3 10:2 micd_lvl [8:0] 0_0000_ 0000 mic detect level (indicates the measured impedance) [8] = >475 ohm, <30k ohm [7] = not used [6] = not used [5] = 375 ohm [4] = 155 ohm [3] = 73 ohm [2] = 40 ohm [1] = 18 ohm [0] = <3 ohm note that the impedance values quoted assume that a microphone (475ohm- 30kohm) is also present on the micdet pin. 1 micd_valid 0 mic detect data valid 0 = not valid 1 = valid 0 micd_sts 0 mic detect status 0 = no mic/accessory present (impedance is >30k ohm) 1 = mic/accessory is present (impedance is <30k ohm) r3105 (0c21h) misc pad ctrl 2 8 micd_pd 0 micdetn pull-down enable 0 = disabled 1 = enabled on micdet1 (if accdet_src=0) or micdet2 (if accdet_src=1) table 69 microphone detect control the external connections for the microphone detect ci rcuit are illustrated in figure 60. in typical applications, it can be used to det ect a microphone or button press. note that, when using the microphone detect circ uit, it is recommended to use one of the right channel analogue microphone input paths, to ensure best immunity to electr ical transients arising from the external accessory. the voltage reference for the microphone detection is configured using the micd_bias_src register, as described in table 69. the microphone detection function will automatically enable the applicable reference when required for micdet impedance measurement.
production data WM5102 w pd, may 2013, rev 4.0 169 if the selected reference (micbias1, micbias2 or micbias3) is not already enabled (ie. if micb n _ena = 0, where n is 1, 2 or 3 as appropriate), then the applicable micbias source will be enabled for short periods of time only, every time the impedance meas urement is scheduled. to allow time for the micbias source to start-up, a time delay is applied before the measurement is performed; this is configured using the micd_bias_star ttime register, as described in table 69. the micd_bias_starttime register should be set to 16ms or more if micb n _rate = 1 (pop-free start-up / shut-down). the micd_bias_starttime r egister should be set to 0.25ms or more if micb n _rate = 0 (fast start-up / shut-down). if the selected reference is not enabled continuously (ie. if micb n _ena = 0), then the applicable micbias discharge bit (micb n _disch) should be set to 0. the micbias sources are configured using the regi sters described in the ?charge pumps, regulators and voltage reference? section. figure 60 microphone and accessory detect interface the micd_lvl_sel [7:0] register bits allow each of the impedance measurement levels to be enabled or disabled independently. this allows the func tion to be tailored to the particular application requirements. if one or more bits within the micd_lvl_sel regi ster is set to 0, then the corresponding impedance level will be disabled. any measured impedance which lies in a disabled level will be reported as the next lowest, enabled level. for example, the micd_lvl_sel [2] bit enables the detection of impedances around 73 ? . if micd_lvl_sel [2] = 0, then an external impedance of 73 ? will not be indicated as 73 ? but will be indicated as 40 ? ; this would be reported in the micd_lvl register as micd_lvl [2] = 1. with all measurement levels enabled, the WM5102 can detect the presence of a typical microphone and up to 6 push-buttons. the microphone detect functi on is specifically designed to detect a video accessory (typical 75 ? ) load if required. see ?applications information? for typical recommended external components for microphone, video or push-button accessory detection. the microphone detection circuit assumes that a 2.2k ? (2%) resistor is connected to the selected micbias reference, as illustrated. different resist or values will lead to inaccuracy in the impedance measurement. the measurement accuracy of the microphone detec t function is assured whenever the connected load is within the applicable limits specified in t he ?electrical characteristics?. note that a 2.2k ? (2%)
WM5102 production data w pd, may 2013, rev 4.0 170 resistor must also be connected between micdet and the selected micbias reference. note that the connection of a microphone will change the measured impedance on the micdet pin; see ?applications information? for re commended components for typical applications. the measurement time varies between 100 ? s and 500 ? s according to the impedance of the external load. a high impedance will be measured faster than a low impedance. the timing of the microphone detect function is illust rated in figure 61. two different cases are shown, according to whether micbias n is enabled periodically by the impedance measurement function (micb n _ena=0), or is enabled at all times (micb n _ena=1). figure 61 microphone and accessory detect timing headphone detect the WM5102 headphone detection circui t measures the impedance of an external headphone load. this feature can be used to set different gain levels or to apply other configuration settings according to the type of load connected. separate monito r pins are provided for headphone detection on the left and right channels of hpout1. headphone detection may only be selected on one channel at a time. the available channels are the hpdetl pin or the hpdetr pin. the sele cted channel is determined by the accdet_mode register as described in table 70. the WM5102 can only support one headphone or microphone detection function at any time. when the detection function is not in use, it is recommended to set accdet_mode=00. the impedance measurement range is configured usi ng the hp_impedance_range register. this register should be set in accordanc e with the expected load impedance.
production data WM5102 w pd, may 2013, rev 4.0 171 headphone detection on the selected channel is commanded by writing a ?1? to the hp_poll register bit. when headphone detection is commanded, the WM5102 us es an adjustable current source to determine the connected impedance. a sweep of measurem ent currents is applied. the rate of this sweep can be adjusted using the hp_rate register. to avoid audible clicks, the default step size should always be used (hp_rate = 0). the timing of the current source ramp is also controlled by the hp_holdtime register. it is recommended that the default setting (001b) be used for this parameter. completion of the headphone detection is indicated by t he hp_done register bit. when this bit is set, the measured load impedance can be read from the hp _lvl register. note that, after the hp_done bit has been asserted, it will remain assert ed until a subsequent headphone detection measurement is commanded. the headphone detection result (hp_lvl) is restricted to values that are close to the range defined by the hp_impedance_range register. if the hp_lvl register reports an impedance that is outside the selected range, then it is recommended to adjust the hp_impedance_range value and repeat the measurement. for minimum measur ement time, the lowest impedance range (hp_impedance_range=00) should be selected in the first instance. the headphone detection function is an input to the inte rrupt control circuit and can be used to trigger an interrupt event on completion of the headphone detection - see ?interrupts?. the headphone detection function can also generate a gp io output, providing an external indication of the headphone detection. see ?general purpose input / output? to configure a gpio pin for this function. the register fields associated with headphone dete ction are described in table 70. the external circuit configuration is illustrated in figure 62. register address bit label default description r659 (0293h) accessory detect mode 1 1:0 accdet_mode [1:0] 00 accessory detect mode select 00 = micdet measurement 01 = hpdetl measurement 10 = hpdetr measurement 11 = micdet note that the micdet function is provided on the micdet1 or micdet2 pins, depending on the accdet_src register bit. r667 (029bh) headphone detect 1 10:9 hp_impedance _range [1:0] 00 headphone detect range 00 = 4 ohms to 30 ohms 01 = 8 ohms to 100 ohms 10 = 100 ohms to 1k ohms 11 = 1k ohms to 10k ohms 7:5 hp_holdtime [2:0] 001 headphone detect hold time (selects the hold time between ramp up and ramp down of the headphone detect current source.) 000 = 31.25us 001 = 125us 010 = 500us 011 = 2ms 100 = 8ms 101 = 16ms 110 = 24ms 111 = 32ms 1 hp_rate 0 headphone detect ramp rate 0 = normal rate 1 = fast rate
WM5102 production data w pd, may 2013, rev 4.0 172 register address bit label default description 0 hp_poll 0 headphone detect enable write 1 to start hp detect function r668 (029ch) headphone detect 2 15 hp_done 0 headphone detect status 0 = hp detect not complete 1 = hp detect done 14:0 hp_lvl [14:0] 0000h headphone detect level lsb = 1 ohm valid from 4..10k ohm 4 = 4ohm or less 5 = 5 ohm 6 = 6 ohm ?. 10,000 = 10k ohm or more note that hp_lvl is restricted to values close to the range selected by hp_impedance_range. if hp_lvl reports an impedance outside the selected range, then the range should be adjusted and the measurement repeated. a result of 0 ohms may be reported if the measurement is less than the minimum value for the selected range. table 70 headphone detect control figure 62 headphone detect interface the external connections for the headphone detect circ uit are illustrated in figure 62. note that only the hpout1l or hpout1r headphone outputs should be connected to hpdetl or hpdetr pins - impedance measurement is not supported on hp out2l, hpout2r, epoutp or epoutn. note that, where external resistors are connected in series with the headphone load, as illustrated, it is recommended that the hpdet n connection is to the headphone side of the resistors. if the hpdet n connection is made to the WM5102 ?end? of thes e resistors, this will lead to a corresponding offset in the measured impedance. note that the measurement accuracy of the headphone detect function may be up to +/-30%. under default conditions, the meas urement time varies between 17ms and 61ms according to the impedance of the external load. a high impedance will be measured faster than a low impedance.
production data WM5102 w pd, may 2013, rev 4.0 173 low power sleep configuration the WM5102 supports a low-power ?sleep? mode, w here most functions are disabled, and power consumption is minimised. a sele ctable ?wake-up? event can be confi gured to return the device to full operation and/or execute a specific respons e to the particular wake-up condition. a wake-up event is triggered via hardware input pi n(s); in typical applications, these inputs are associated with jack insert (via the jackdet digita l input) or external push-button detection (via the gpio5 digital input). the WM5102 enters sleep mode when ldo1 is dis abled (by setting ldo1_ena=0), causing the dcvdd supply to be removed. the avdd, dbvdd1 and ldovdd supplies must be present, and the ldoena pin held low, allowing the WM5102 registers to control ldo1. note that it is assumed that dcvdd is supp lied by ldo1; see ?charge pumps, regulators and voltage reference? for specific control requi rements where dcvdd is not powered from ldo1. sleep mode the WM5102 enters sleep mode when ldo1 is disabled (by setting ldo1_ena=0). in this case, the dcvdd supply is disabled, and most of the digital core (and control registers) are held in reset. selected functions and control registers are mainta ined via an ?always-on? internal supply domain in sleep mode. the ?always-on? control registers are lis ted in table 71. these registers are maintained (ie. not reset) in sleep mode. note that the control interface is not supported in sleep mode. read/write access to the ?always-on? registers is not possible in sleep mode. register address label reference 40h wkup_micd_clamp_fall see table 74 wkup_micd_clamp_rise wkup_gp5_fall wkup_gp5_rise wkup_jd1_fall wkup_jd1_rise 41h wseq_ena_micd_clamp_fal l see table 75 wseq_ena_micd_clamp_ris e wseq_ena_gp5_fall wseq_ena_gp5_rise wseq_ena_jd1_fall wseq_ena_jd1_rise 66h wseq_micd_clamp_rise_ind ex see ?control write sequencer? 67h wseq_micd_clamp_fall_ind ex 68h wseq_gp5_rise_index 69h wseq_gp5_fall_index 6ah wseq_jd1_rise_index 6bh wseq_jd1_fall_index 100h clk_32k_ena see ?clocking and sample rates? clk_32k_src 210h ldo1_vsel see ?charge pumps, regulators and voltage reference? ldo1_disch ldo1_bypass ldo1_ena
WM5102 production data w pd, may 2013, rev 4.0 174 register address label reference 02a2h micd_clamp_mode see ?external accessory detection? 02d3h jd1_ena see ?external accessory detection? 0c04h gp5_dir see ?general purpose input / output? gp5_pu gp5_pd gp5_pol gp5_op_cfg gp5_db gp5_lvl gp5_fn 0c0fh irq_pol see ?interrupts? irq_op_cfg 0c10h gp_dbtime see ?general purpose input / output? 0c20h ldo1ena_pd see ?charge pumps, regulators and voltage reference? mclk2_pd see ?clocking and sample rates? reset_pu see ?hardware reset, software reset, wake-up, and device id? 0d0fh im_irq1 see ?interrupts? 0d1fh im_irq2 0d50h micd_clamp_fall_trig_sts see table 73 micd_clamp_rise_trig_sts gp5_fall_trig_sts gp5_rise_trig_sts jd1_fall_trig_sts jd1_rise_trig_sts 0d51h micd_clamp_fall_eint1 see ?interrupts? micd_clamp_rise_eint1 gp5_fall_eint1 gp5_rise_eint1 jd1_fall_eint1 jd1_rise_eint1 0d52h micd_clamp_fall_eint2 see ?interrupts? micd_clamp_rise_eint2 gp5_fall_eint2 gp5_rise_eint2 jd1_fall_eint2 jd1_rise_eint2 0d53h im_micd_clamp_fall_eint1 see ?interrupts? im_micd_clamp_rise_eint1 im_gp5_fall_eint1 im_gp5_rise_eint1 im_jd1_fall_eint1 im_jd1_rise_eint1 0d54h im_micd_clamp_fall_eint2 see ?interrupts? im_micd_clamp_rise_eint2 im_gp5_fall_eint2 im_gp5_rise_eint2 im_jd1_fall_eint2 im_jd1_rise_eint2 0d56h micd_clamp_db see ?external accessory detection? jd1_db
production data WM5102 w pd, may 2013, rev 4.0 175 register address label reference 3000h to 31ffh wseq_data_widthn see ?control write sequencer? wseq_addrn wseq_delayn wseq_data_startn wseq_datan table 71 sleep mode ?always-on? control registers the ?always-on? digital input / output pins are listed in table 72. all other digital input pins will have no effect in sleep mode. the irq output is normally de-asserted in sleep mode. note that, in sleep mode, the irq output can only be asserted in response to the jd1 or gp5 control signals (these described in the following section). if the irq output is asserted in sleep mode, it can only be de-asserted after a wake-up transition. pin name description reference ldoena enable pin for ldo1 see ?charge pumps, regulators and voltage reference? reset digital reset input (active low) see ?hardware reset, software reset, wake-up, and device id? mclk2 master clock 2 see ?clocking and sample rates? gpio5 general purpose pin gpio5 s ee ?general purpose input / output? irq interrupt request (irq) output see ?interrupts? table 72 sleep mode ?always-on? digital input pins a wake-up transition is triggered using the jd1 or gp5 control signals (defined below). it is assumed that dcvdd is supplied by ldo1 . the avdd, dbvdd1 and ldovdd supplies must be present, and the ldoena pin held low, allowing t he WM5102 registers to control ldo1. see ?charge pumps, regulators and voltage reference? for spec ific control requirements where dcvdd is not powered from ldo1. note that a logic ?1? applied to the ldoena pin w ill also cause a wake-up transition. in this event, however, the configurable wake-up event s (described below) are not applicable. sleep control signals - jd1, gp5, micdet clamp the internal control signals jd1 and gp5 are pr ovided to support the low-power sleep mode. the micdet clamp status is controlled by a selectabl e logic function, derived from jd1 and/or gp5. a rising or falling edge of these signals can be used to trigger a wake-up transition (ie. exit from sleep mode). the jd1, gp5 and micdet clamp status signals c an also be used to trigger the control write sequencer and/or the interrupt controller. note that it is possible to enable more than one re sponse from these control signals. for example, a particular edge transition could trigger a wake-up transition, and also a control write sequence. the jd1, gp5 and micdet clamp status signals are de scribed in this section. the wake-up, write sequencer, and interrupt actions are descr ibed in the sections that follow. the jd1 signal is derived from the jack detect func tion (see ?external accessory detection?). this input can be used to trigger wake-up or other actions in response to a jack insertion or jack removal detection. when the jd1 signal is enabled, it indicates the stat us of the jackdet input pin. see table 67 for details of the associated control registers.
WM5102 production data w pd, may 2013, rev 4.0 176 the gp5 signal is derived from the gpio5 input pin (see ?general purpos e input / output?). this input can be used to trigger wake-up or other actions in response to a logic level input detected on the gpio5 pin. when using the gp5 signal, the gpio5 pin must be configured as a gpio input (gp5_dir=1, gp5_fn=01h). an internal pull-up or pull-down resi stor may be enabled on the gpio5 pin if required. the gpio pin control registers are defined in table 76. the micdet clamp status is controlled by the jd1 and/or gp5 signals (see ?external accessory detection?). the configurable logi c provides flexibility in select ing the appropriate conditions for activating the micdet clamp. the cl amp status can be used to trigger wake-up or other actions in response to a jack insertion or jack removal detection. the micdet clamp function is c onfigured using the micd_clamp_mode register, as described in table 68. whenever a rising or falling edge is detected on jd 1, gp5 or micdet clamp status, the WM5102 will assert the respective trigger status (_trig_sts) bi t. the trigger status bits are latching fields and, once they are set, they are not reset until a ?1? is written to the respective register bit(s). the jd1, gp5 and micdet clamp trigger st atus bits are described in table 73. the trigger status bits can be used to control wake-up and write sequencer actions. the jd1, gp5 and micdet clamp signals are inputs to the interrupt c ontroller. each of these functions is described in the following sections. register address bit label default description r3408 (0d50h) aod wkup and trig 7 micd_clamp_fall_t rig_sts 0 micdet clamp trigger status (falling edge triggered) note: cleared when a ?1? is written 6 micd_clamp_rise_t rig_sts 0 micdet clamp trigger status (rising edge triggered) note: cleared when a ?1? is written 5 gp5_fall_trig_sts 0 gp5 trigger status (falling edge triggered) note: cleared when a ?1? is written 4 gp5_rise_trig_sts 0 gp5 trigger status (rising edge triggered) note: cleared when a ?1? is written 3 jd1_fall_trig_sts 0 jd1 trigger status (falling edge triggered) note: cleared when a ?1? is written 2 jd1_rise_trig_sts 0 jd1 trigger status (rising edge triggered) note: cleared when a ?1? is written table 73 jd1, gp5 and micdet clamp trigger status registers note that the de-bounce function on all inputs (i ncluding jd1, gp5 and mi cdet clamp status) use the 32khz clock (see ?clocking and sample rate s?). the 32khz clock must be enabled whenever input de-bounce functions are required. note that the mclk2 input pin is on the ?alw ays-on? domain, and is supported in sleep mode. (mclk1 input is not supported in sleep mode.) if input de-bounce is enabled in sleep m ode, the 32khz clock must use mclk2 (direct) input as its source (clk_32k_src = 01).
production data WM5102 w pd, may 2013, rev 4.0 177 wake-up transition a wake-up transition (exit from sleep) can be associ ated with any of the jd1, gp5 or micdet clamp trigger status bits. this is selected usi ng the register bits described in table 74. register address bit label default description r64 (0040h) wake control 7 wkup_micd_clamp_ fall 0 micdet clamp (falling) wake-up select 0 = disabled 1 = enabled 6 wkup_micd_clamp_ rise 0 micdet clamp (rising) wake-up select 0 = disabled 1 = enabled 5 wkup_gp5_fall 0 gp5 (falling) wake-up select 0 = disabled 1 = enabled 4 wkup_gp5_rise 0 gp5 (rising) wake-up select 0 = disabled 1 = enabled 3 wkup_jd1_fall 0 jd1 (falling) wake-up select 0 = disabled 1 = enabled 2 wkup_jd1_rise 0 jd1 (rising) wake-up select 0 = disabled 1 = enabled table 74 jd1, gp5 and micdet clamp wake-up control registers when a valid ?wake-up? event is detected, the WM5102 will enable ldo1 (and dcvdd), and a user- configurable boot sequence is executed (see ?hardware reset, software reset, wake-up, and device id?). note that the trigger status (_trig_sts) bits are latching fields. care is required when resetting these bits, to ensure the intended device behaviour - resetting the _trig_st s register(s) may cause ldo1 (and dcvdd) to be disabled. for normal device operation following a ?wake-up? tr ansition, the ldo1_ena register must be set before the _trig_sts bit(s) are reset. (note that further options are described in the next section.)
WM5102 production data w pd, may 2013, rev 4.0 178 write sequence control a control write sequence can be associated with any of the jd1, gp5 or micdet clamp trigger status bits. this is selected using t he register bits described in table 75. note that the jd1 and gp5 trigger status bits c an be used to trigger the control write sequencer at any time. this feature may be used during normal operation, or immediately following a wake-up transition. register address bit label default description r65 (0041h) sequence control 7 wseq_ena_micd_cl amp_fall 0 micdet clamp (falling) write sequencer select 0 = disabled 1 = enabled 6 wseq_ena_micd_cl amp_rise 0 micdet clamp (rising) write sequencer select 0 = disabled 1 = enabled 5 wseq_ena_gp5_fal l 0 gp5 (falling) write sequencer select 0 = disabled 1 = enabled 4 wseq_ena_gp5_ris e 0 gp5 (rising) write sequencer select 0 = disabled 1 = enabled 3 wseq_ena_jd1_fall 0 jd1 (falling) write sequencer select 0 = disabled 1 = enabled 2 wseq_ena_jd1_rise 0 jd1 (rising) write sequencer select 0 = disabled 1 = enabled table 75 jd1, gp5 and micdet clamp write sequencer control registers when a valid ?write sequencer? control event is detected, the respective control sequence will be scheduled. see ?control write sequencer? for further details. note that the trigger status (_trig_sts) bits are latching fields. care is required when resetting these bits, to ensure the intended device behaviour - resetting the _trig_st s register(s) may cause ldo1 (and dcvdd) to be disabled. a valid clock (sysclk) must be enabled whenever a control write sequence is scheduled. if the jd1, gp5 or micdet clamp trigger status bi ts are associated with the control write sequencer (using the register bits in table 75) and also confi gured as wake-up events (using the register bits in table 74), then the boot sequence must be progra mmed to configure and enable sysclk. (note that the default sysclk frequency must be used in this case.) the boot sequence (see ?hardware reset, softwar e reset, wake-up, and device id?) is scheduled as part of the wake-up transition, and provides the capability to configure sysclk (and other register settings) prior to the control write sequencer being triggered. note that, if the control write sequencer is triggered during normal operation, then sysclk will typically be already available, and no additional requirements will apply.
production data WM5102 w pd, may 2013, rev 4.0 179 to return to sleep mode following a wake-up / write sequence, the last step of the control sequence must be to write ?1? to the applicable trigger status bit(s). the _trig_sts bi t(s) will be reset, ldo1 will be disabled, and the WM5102 will be in sleep mode. (the ldo1_ena bit must be set to 0, and the ldoena pin must not be asserted.) to remain ?on? at the end of a wake-up / write sequence, the control sequence must write ?1? to the ldo1_ena bit before resetting the trigger status bit(s). when the control write sequencer is triggered dur ing normal operation, it can be programmed to select the sleep mode by writing ?0? to the ldo1_ena bit. (the ldoena pin must not be asserted.) see ?charge pumps, regulators and voltage reference? for details of the ldo1_ena control bit. interrupt control an interrupt request (irq) event can be associat ed with the jd1, gp5 or micdet clamp signals. separate ?mask? bits are provided to enable ir q events on the rising and/or falling edges of each signal. see ?interrupts? for further details.
WM5102 production data w pd, may 2013, rev 4.0 180 general purpose input / output the WM5102 provides a number of gpio functions to enable interf acing and detection of external hardware and to provide logic outputs to other dev ices. the gpio input f unctions can be used to generate an interrupt (irq) event. the gpio and inte rrupt circuits support the following functions: ? digital audio interface function (aifntxlrclk) ? logic input / button detect (gpio input) ? logic ?1? and logic ?0? output (gpio output) ? interrupt (irq) status output ? dsp status flag (dsp irqn) and ram status output ? clock output ? frequency locked loop (fll) status output ? frequency locked loop (fll) clock output ? pulse width modulation (pwm) signal output ? headphone detection status output ? microphone / accessory detection status output ? asynchronous sample rate converter (asrc) lock status and configuration error output ? control write sequencer status output ? boot sequence status output ? over-temperature status output ? dynamic range control (drc) status output ? control interface error status output ? clocking error status output ? digital audio interface confi guration error status output note that the gpio pins are referenced to diffe rent power domains (dbvdd1, dbvdd2 or dbvdd3), as noted in the ?pin description? section. in addition to the functions described in this secti on, the gpio5 pin can be configured as an input to the control write sequencer (see ?control write s equencer?). see also table 75 for details of the associated register control fields. the gpio5 pin is one of the ?always on? digital input / output pins and c an be used as a ?wake-up? input in the low-power ?sleep? mode. the gpio5 pin can also be used as an input to the micdet clamp function, supporting additional functionality relating to jack insertion or jack removal events see ?low power sleep configuration? for further details.
production data WM5102 w pd, may 2013, rev 4.0 181 gpio control for each gpio, the selected function is determined by the gp n _fn field, where n identifies the gpio pin (1, 2, 3, 4 or 5). the pin direction, set by gp n _dir, must be set according to function selected by gp n _fn. when a pin is configured as a gpio input (gp n _dir = 1, gp n _fn = 01h), the logic level at the pin can be read from the respective gp n _lvl bit. note that gp n _lvl is not affected by the gp n _pol bit. a de-bounce circuit can be enabled on any gpio input, to avoid false event triggers. this is enabled on each pin by setting the respective gp n _db bit. the de-bounce circuit us es the 32khz clock, which must be enabled whenever input de-bounce functi ons are required. the de-bounce time is configurable using the gp_dbtime register. see ?clocking and sample rates? for further details of the WM5102 clocking configuration. each of the gpio pins is an input to the interrupt control circuit and can be us ed to trigger an interrupt event. an interrupt event is triggered on the risi ng and falling edges of the gpio input. the associated interrupt bit is latched once set; it can be polled at any time or used to control the irq signal. see ?interrupts? for more details of the interrupt event handling. when a pin is configured as a gpio input, internal pull-up and pull-down resistors may be enabled using the gp n _pu and gp n _pd fields; this allows greater flexib ility to interface with different signals from other devices. (note that, if the pin is configured as an output, or if gp n _pu and gp n _pd are both set for any gpio pin, then the pull-up and pull-down will be disabled.) when a pin is configured as a gpio output (gp n _dir = 0, gp n _fn = 01h), its level can be set to logic 0 or logic 1 using the gp n _lvl field. note that the gp n _lvl registers are ?write only? when the respective gpio pin is configured as an output. when a pin is configured as an output (gp n _dir = 0), the polarity can be inverted using the gp n _pol bit. when gp n _pol = 1, then the selected output function is inverted. in the case of logic level output (gp n _fn = 01h), the external output will be the opposite logic level to gp n _lvl when gp n _pol = 1. a gpio output can be either cmos driven or open drain. this is selected on each pin using the respective gp n _op_cfg bit. the register fields that control the gpio pins are described in table 76.
WM5102 production data w pd, may 2013, rev 4.0 182 register address bit label default description r3072 (0c00h) gpio1 ctrl to r3076 (0c04h) gpio5 ctrl 15 gpn_dir 1 gpion pin direction 0 = output 1 = input 14 gpn_pu 0 gpion pull-up enable 0 = disabled 1 = enabled (only valid when gpn_dir=1) 13 gpn_pd 1 gpion pull-down enable 0 = disabled 1 = enabled (only valid when gpn_dir=1) 11 gpn_lvl 0 gpion level. write to this bit to set a gpio output. read from this bit to read gpio input level. for output functions only, when gpn_pol is set, the register is the opposite logic level to the external pin. note that the gp n _lvl register is ?write only? when gp n _dir=0. 10 gpn_pol 0 gpion output polarity select 0 = non-inverted (active high) 1 = inverted (active low) 9 gpn_op_cfg 0 gpion output configuration 0 = cmos 1 = open drain 8 gpn_db 1 gpion input de-bounce 0 = disabled 1 = enabled 6:0 gpn_fn [6:0] 01h gpion pin function (see table 77 for details) r3088 (0c10h) gpio debounce config 15:12 gp_dbtime [3:0] 0001 gpio input de-bounce time 0h = 100us 1h = 1.5ms 2h = 3ms 3h = 6ms 4h = 12ms 5h = 24ms 6h = 48ms 7h = 96ms 8h = 192ms 9h = 384ms ah = 768ms bh to fh = reserved note: n is a number (1, 2, 3, 4 or 5) that identifies the individual gpio. table 76 gpio control
production data WM5102 w pd, may 2013, rev 4.0 183 gpio function select the available gpio functions are described in table 77. the function of each gpio is set using the gp n _fn register, where n identifies the gpio pin (1, 2, 3, 4 or 5). note that the respective gp n _dir must also be set according to whether the function is an input or output. gpn_fn description comments 00h gpio1 - aif1txlrclk gpio2 - aif2txlrclk gpio3 - aif3txlrclk gpio4 - reserved gpio5 - reserved alternate audio interface c onnections for aif1, aif2 and aif3 01h button detect input / logic level output gpn_dir = 0: gpio pin logic level is set by gpn_lvl. gpn_dir = 1: button detect or logic level input. 02h irq1 output interrupt (irq1) output 0 = irq1 not asserted 1 = irq1 asserted 03h irq2 output interrupt (irq2) output 0 = irq2 not asserted 1 = irq2 asserted 04h opclk clock output configurable clock output derived from sysclk 05h fll1 clock clock output from fll1 06h fll2 clock clock output from fll2 07h reserved 08h pwm1 output configurable puls e width modulation output pwm1 09h pwm2 output configurable puls e width modulation output pwm2 0ah sysclk underclocked error indicates that an unsupported clocking configuration has been attempted 0 = normal 1 = sysclk underclocking error 0bh asyncclk underclocked error indicates that an unsupported clocking configuration has been attempted 0 = normal 1 = asyncclk underclocking error 0ch fll1 lock indicates fll1 lock status 0 = not locked 1 = locked 0dh fll2 lock indicates fll2 lock status 0 = not locked 1 = locked 0eh reserved 0fh fll1 clock ok indicates fll1 clock ok status 0 = fll1 clock output is not active 1 = fll1 clock output is active 10h fll2 clock ok indicates fll2 clock ok status 0 = fll2 clock output is not active 1 = fll2 clock output is active 11h reserved 12h headphone detect indicates headphone detection status 0 = headphone detect not complete 1 = headphone detect complete
WM5102 production data w pd, may 2013, rev 4.0 184 gpn_fn description comments 13h microphone detect microphone detect (micdet accessory) irq output a single 31 ? s pulse is output whenever an accessory insertion, removal or impedance change is detected. 14h reserved 15h write sequencer status indicates write sequencer status 0 = busy (sequence in progress) 1 = idle (sequence completed) 16h control interface address error indicates control interface address error 0 = normal 1 = control interface address error 17h reserved 18h reserved 19h reserved 1ah asrc1 lock indicates asrc1 lock status 0 = not locked 1 = locked 1bh asrc2 lock indicates asrc2 lock status 0 = not locked 1 = locked 1ch asrc configuration error indica tes asrc configuration error 0 = asrc configuration ok 1 = asrc configuration error 1dh drc1 signal detect indicates drc1 signal detect status 0 = signal threshold not exceeded 1 = signal threshold exceeded 1eh drc1 anti-clip active indicates drc1 anti-clip status 0 = anti-clip is not active 1 = anti-clip is active 1fh drc1 decay active indicates drc1 decay status 0 = decay is not active 1 = decay is active 20h drc1 noise gate active indicates drc1 noise gate status 0 = noise gate is not active 1 = noise gate is active 21h drc1 quick release active indicates drc1 quick release status 0 = quick release is not active 1 = quick release is active 22h reserved 23h reserved 24h reserved 25h reserved 26h reserved 27h mixer dropped sample error indicates a dropped sample in the digital core mixers 0 = normal 1 = mixer dropped sample error 28h aif1 configuration error indica tes aif1 configuration error 0 = aif1 configuration ok 1 = aif1 configuration error 29h aif2 configuration error indica tes aif2 configuration error 0 = aif2 configuration ok 1 = aif2 configuration error 2ah aif3 configuration error indica tes aif3 configuration error 0 = aif3 configuration ok 1 = aif3 configuration error
production data WM5102 w pd, may 2013, rev 4.0 185 gpn_fn description comments 2bh speaker shutdown temperature indicates shutdown temperature status 0 = temperature is below shutdown level 1 = temperature is above shutdown level 2ch speaker warning temperature indicates warning temperature status 0 = temperature is below warning level 1 = temperature is above warning level 2dh underclocked error indicates insufficient sysclk or asyncclk cycles for one or more of the selected signal paths or signal processing functions. increasing the sysclk or asyncclk frequency (as applicable) should allow the selected configuration to be supported. 0 = normal 1 = underclocked error 2eh overclocked error indicates that an unsupported device c onfiguration has been attempted, as the clocking requirements of the requested configuration ex ceed the device limits. 0 = normal 1 = overclocked error 2fh reserved 30h reserved 31h reserved 32h reserved 33h reserved 34h reserved 35h dsp irq1 flag dsp status flag (dsp_irq1) output 0 = dsp_irq1 not asserted 1 = dsp_irq1 asserted 36h dsp irq2 flag dsp status flag (dsp_irq2) output 0 = dsp_irq2 not asserted 1 = dsp_irq2 asserted 37h reserved 38h reserved 39h reserved 3ah reserved 3bh reserved 3ch reserved 3dh opclk async clock output configurable clock output derived from asyncclk 3eh reserved 3fh reserved 40h reserved 41h reserved 42h reserved 43h reserved 44h boot done boot status 0 = busy (boot-up in progress) 1 = idle (boot-up completed) 45h dsp1 ram ready dsp1 ram status 0 = not ready 1 = ready 46h reserved 47h reserved 48h reserved 49h reserved
WM5102 production data w pd, may 2013, rev 4.0 186 gpn_fn description comments 4ah reserved 4bh sysclk_ena status sysclk_ena status 0 = sysclk_ena is enabled 1 = sysclk_ena is disabled 4ch async_clk_ena status async_clk_ena status 0 = async_clk_ena is enabled 1 = async_clk_ena is disabled table 77 gpio function select digital audio interface function (aifntxlrclk) gp n _fn = 00h. the WM5102 provides three digital audio interfaces (aif1, aif2 and aif3). under default conditions, the input (rx) and output (t x) paths of each interface use the respective aifnrxlrclk signal as the frame synchronisation cl ock. if desired, the output (tx) interface can be configured to use a separate frame clock, aifn txlrclk, using the aifntx_lrclk_src registers as described in ?digital audio interface control?. the aifntxlrclk function is selected on the respecti ve gpio pin by setting the gpio registers as described in ?gpio control?. button detect (gpio input) gp n _fn = 01h. button detect functionality can be selected on any gpio pin by setting the respective gpio registers as described in ?gpio control?. the same functi onality can be used to support a jack detect input function. it is recommended to enable the gpio input de-bounce feature when using gpios as button input or jack detect input. the gp n _lvl fields may be read to determine the logic levels on a gpio input, after the selectable de-bounce controls. note that gp n _lvl is not affected by the gp n _pol bit. the de-bounced gpio signals are also inputs to the in terrupt control circuit. an interrupt event is triggered on the rising and falling edges of the gpio input. the associated interrupt bits are latched once set; it can be polled at any time or used to control the irq signal. see ?interrupts? for more details of the interrupt event handling.
production data WM5102 w pd, may 2013, rev 4.0 187 logic ?1? and logic ?0? output (gpio output) gp n _fn = 01h. the WM5102 can be programmed to drive a logic high or logic low level on any gpio pin by selecting the ?gpio output? function as described in ?gpio control?. the output logic level is selected using the respective gp n _lvl bit. note that the gp n _lvl registers are ?write only? when the respective gpio pin is configured as an output. the polarity of the gpio output can be inverted using the gp n _pol registers. if gp n _pol=1, then the external output will be the opposite logic level to gp n _lvl. interrupt (irq) status output gp n _fn = 02h, 03h. the WM5102 has an interrupt controller which can be used to indicate when any selected interrupt events occur. an interrupt can be generated by any of the events described throughout the gpio function definition above. individual interrupts may be masked in order to configure the interrupt as required. see ?interrupts? for further details. the interrupt controller supports two separate interrupt request (irq) outputs. the irq1 or irq2 status may be output directly on any gpio pin by setting the respective gpio registers as described in ?gpio control?. note that the irq1 status is output on the irq pin at all times. dsp status flag (dsp irqn) output gp n _fn = 35h, 36h, 45h. the WM5102 supports two dsp status flags as outputs from the dsp block. these are configurable within the dsp to provide external indication of the required function(s). a status flag indicating the dsp1 ram status is also supported. see ?dig ital core? for more details of the dsp. the dsp status and dsp ram ready flags may be output directly on any gpio pin by setting the respective gpio registers as described in ?g pio control?. the dsp status and dsp ram ready outputs are described in table 78. the dsp status flags are inputs to the interrupt c ontroller circuit. an interrupt event is triggered on the rising edge of the dsp status (dsp_irqn) fl ags or dsp ram ready flags. the associated interrupt bits are latched once set; they can be poll ed at any time or used to control the irq signal. see ?interrupts? for more details of the interrupt event handling. gpn_fn description comments 35h dsp status (dsp_irq1) external indication of dsp_irq1_sts 36h dsp status (dsp_irq2) external indication of dsp_irq2_sts 45h dsp1 ram ready indicates dsp1 ram ready status table 78 dsp status and ram ready indications
WM5102 production data w pd, may 2013, rev 4.0 188 opclk and opclk_async clock output gp n _fn = 04h, 3dh. a clock output (opclk) derived from sysclk can be output on any gpio pin. the opclk frequency is controlled by opclk_div and opcl k_sel. the opclk output is enabled using the opclk_ena register, as described in table 79. a clock output (opclk_async) derived from asyncclk can be output on any gpio pin. the opclk_async frequency is controlled by opclk_async_div and opclk_async_sel. the opclk_async output is enabled using the opclk_async_ena register it is recommended to disable the clock output (opclk_ena=0 or opclk_async_ena=0) before making any change to the respective op clk_div or opclk_async_div register. the opclk or opclk_async clock outputs can be output directly on any gpio pin by setting the respective gpio registers as described in ?gpio control?. note that the opclk source frequency cannot be higher than the sysclk frequency. the opclk_async source frequency cannot be higher than the asyncclk frequency. the maximum output frequency supported for gpio output is not ed in the ?electrical characteristics?. see ?clocking and sample rates? for more details of the system clocks (sysclk and asyncclk). register address bit label default description r329 (0149h) output system clock 15 opclk_ena 0 opclk enable 0 = disabled 1 = enabled 7:3 opclk_div [4:0] 00h opclk divider 00h = divide by 1 01h = divide by 1 02h = divide by 2 03h = divide by 3 ? 1fh = divide by 31 2:0 opclk_sel [2:0] 000 opclk source frequency 000 = 6.144mhz (5.6448mhz) 001 = 12.288mhz (11.2896mhz) 010 = 24.576mhz (22.5792mhz) 011 = 49.152mhz (45.1584mhz) all other codes are reserved the frequencies in brackets apply for 44.1khz-related sysclk rates only (ie. sample_rate_n = 01xxx). the opclk source frequency must be less than or equal to the sysclk frequency. r330 (014ah) output async clock 15 opclk_async_ ena 0 opclk_async enable 0 = disabled 1 = enabled 7:3 opclk_async_ div [4:0] 00h opclk_async divider 00h = divide by 1 01h = divide by 1 02h = divide by 2 03h = divide by 3 ? 1fh = divide by 31
production data WM5102 w pd, may 2013, rev 4.0 189 register address bit label default description 2:0 opclk_async_ sel [2:0] 000 opclk_async source frequency 000 = 6.144mhz (5.6448mhz) 001 = 12.288mhz (11.2896mhz) 010 = 24.576mhz (22.5792mhz) 011 = 49.152mhz (45.1584mhz) all other codes are reserved the frequencies in brackets apply for 44.1khz-related asyncclk rates only (ie. async_sample_rate_n = 01xxx). the opclk_async source frequency must be less than or equal to the asyncclk frequency. table 79 opclk and opclk_async control frequency locked loop (fll) status output gp n _fn = 0ch, 0dh, 0fh, 10h. the WM5102 supports fll status flags, which may be used to control other events. see ?clocking and sample rates? for more details of the fll. the ?fll clock ok? signals indicate that the respec tive fll has started up and is providing an output clock. the ?fll lock? signals indicate whether fll lock has been achieved. the fll clock ok and fll lock signals may be output directly on any gpio pin by setting the respective gpio registers as described in ?gpio control?. the fll clock ok and fll lock signals are inputs to the interrupt controller circuit. an interrupt event is triggered on the rising and falling edges of t hese signals. the associated interrupt bits are latched once set; they can be polled at any time or us ed to control the irq signal. see ?interrupts? for more details of the interrupt event handling. frequency locked loop (fll) clock output gp n _fn = 05h, 06h. clock outputs derived from the flls may be output on any gpio pin. the gpio output from each flln (where ?n? is 1 or 2) is controlled by the respective flln_gpclk_div and flln_gpclk_ena registers, as described in table 80. it is recommended to disable the clock output (flln_gpclk_ena=0) before making any change to the respective flln_gpclk_div register. note that the flln_gpclk_div and flln_gpclk_ena registers affect the gpio outputs only; they do not affect the fll frequency. the maximum output frequency supported for gpio output is noted in the ?electrical characteristics?. the frequency locked loop (fll) clock outputs may be output directly on any gpio pin by setting the respective gpio registers as described in ?gpio control?. see ?clocking and sample rates? for more details of the WM5102 system clocking and for details of how to configure the flls.
WM5102 production data w pd, may 2013, rev 4.0 190 register address bit label default description r394 (018ah) fll1 gpio clock 7:1 fll1_gpclk_di v [6:0] 02h fll1 gpio clock divider 00h = divide by 1 01h = divide by 1 02h = divide by 2 03h = divide by 3 ? 3fh = divide by 127 (f gpio = f vco / fll1_gpclk_div) 0 fll1_gpclk_en a 0 fll1 gpio clock enable 0 = disabled 1 = enabled r426 (01aah) fll2 gpio clock 7:1 fll2_gpclk_di v [6:0] 02h fll2 gpio clock divider 00h = divide by 1 01h = divide by 1 02h = divide by 2 03h = divide by 3 ? 3fh = divide by 127 (f gpio = f vco / fll2_gpclk_div) 0 fll2_gpclk_en a 0 fll2 gpio clock enable 0 = disabled 1 = enabled table 80 fll clock output control pulse width modulation (pwm) signal output gp n _fn = 08h, 09h. the WM5102 incorporates two pulse width m odulation (pwm) signal generators which can be enabled as gpio outputs. the duty cycle of each pwm signal can be modulated by an audio source, or can be set to a fixed value us ing a control register setting. the pulse width modulation (pwm) outputs may be out put directly on any gpio pin by setting the respective gpio registers as described in ?gpio control?. see ?digital core? for details of how to configure the pwm signal generators. headphone detection status output gp n _fn = 12h. the WM5102 provides a headphone detecti on circuit on the hpdetl and hpdetr pins to measure the impedance of an external load connected to the headphone outputs. see ?external accessory detection? for further details. a logic signal from the headphone detec tion circuit may be output directly on any gpio pin by setting the respective gpio registers as described in ?g pio control?. this logic signal is set low when a headphone detect measurement is triggered, and is set high when the headphone detect function has completed. a rising edge indicates completion of a headphone detect measurement. the headphone detection circuit is also an input to the interrupt control circuit. an interrupt event is triggered whenever a headphone detection measurement has completed. note that the hpdet_eint flag is also asserted when the headphone detection is init iated. the associated interrupt bit is latched once set; it can be polled at any time or used to control the irq signal. see ?interrupts? for more details of the interrupt event handling.
production data WM5102 w pd, may 2013, rev 4.0 191 microphone / accessory detection status output gp n _fn = 13h. the WM5102 provides an impedance measurement ci rcuit on the micdetn pins to detect the connection of a microphone or other external accesso ry. see ?external accessory detection? for further details. a logic signal from the microphone det ect circuit may be output directly on any gpio pin by setting the respective gpio registers as described in ?gpio c ontrol?. this logic signal is set high for a pulse duration of 31 ? s whenever an accessory insertion, removal or impedance change is detected. the microphone detection circuit is also an input to the interrupt contro l circuit. an interrupt event is triggered whenever an accessory insertion, removal or impedance change is detected. the associated interrupt bit is latched once set; it can be polled at any time or used to control the irq signal. see ?interrupts? for more details of the interrupt event handling. boot done status output gp n _fn = 44h. the WM5102 executes a user-c onfigurable boot sequence following power-on reset (por), hardware reset, software reset or wake-up (from sleep mode). control register writes should not be attempted while the boot sequence is running. for details of the boot sequence, see ?control write sequencer?. the boot_done_sts register bit (see table 113) i ndicates the status of the boot sequence. (when boot_done_sts=1, then the boot sequence is complete.) the boot_done_sts signal may be output directly on any gpio pin by setting the respective gpio registers as described in ?gpio control?. the boot_done_sts signal is also an input to the in terrupt controller circuit. an interrupt event is triggered on the rising edge of this signal. the associ ated interrupt bit is latched once set; it can be polled at any time or used to control the irq signal. see ?interrupts? for more details of the interrupt event handling. asynchronous sample rate converter (asrc) lock status output gp n _fn = 1ah, 1bh. the WM5102 maintains a flag indicating the lock status of the asynchronous sample rate converters (asrcs), which may be used to control other events if required. see ?digital core? for more details of the asrcs. the asrc lock signals may be output directly on any gpio pin by setting the respective gpio registers as described in ?gpio control?. the asrc lock signals are inputs to the interrupt cont rol circuit. an interrupt event is triggered on the rising and falling edges of the asrc lock signals. the associated interrupt bits are latched once set; they can be polled at any time or used to control t he irq signal. see ?interrupts? for more details of the interrupt event handling.
WM5102 production data w pd, may 2013, rev 4.0 192 asynchronous sample rate conver ter (asrc) configuration error status output gpn_fn = 1ch. the WM5102 performs automatic checks to confirm that the asrcs are configured with valid settings. invalid settings include conditions where one of the associated sample rates is higher than 48khz. if an invalid asrc configuration is detected, this can be indicated using the gpio and/or interrupt functions. the asrc configuration error signal may be output dire ctly on any gpio pin by setting the respective gpio registers as described in ?gpio control?. the asrc configuration error signal is an input to the interrupt controller circuit. an interrupt event is triggered on the rising and falling edges of the as rc configuration error signal. the associated interrupt bit is latched once set; it can be polled at any time or used to control the irq signal. see ?interrupts? for more details of the interrupt event handling. over-temperature status output gp n _fn = 2bh, 2ch. the WM5102 incorporates a temperature sensor whic h detects when the device temperature is within normal limits or if the device is approac hing a hazardous temperature condition. the temperature status may be output directly on any gpio pin by setting the respective gpio registers as described in ?gpio control?. any gpio pin can be used to indicate either a warning temperature event or the shutdown temperature event. the warning temperature and shutdown temperature stat us are inputs to the interrupt control circuit. an interrupt event may be triggered on the rising and falling edges of these signals. the associated interrupt bit is latched once set; it can be polled at any time or used to control the irq signal. see ?interrupts? for more details of the interrupt event handling. it is strongly recommended that the speaker driv ers be disabled if the shutdown temperature condition occurs. dynamic range control (drc) status output gp n _fn = 1dh, 1eh, 1fh, 20h, 21h. the dynamic range control (drc) circ uit provides status outputs, wh ich may be used to control other events if required. the drc status flags may be output directly on any gp io pin by setting the respective gpio registers as described in ?gpio control?. the drc st atus outputs are described in table 81. see ?digital core? for more details of the drc. gpn_fn description comments 1dh drc1 signal detect indicates a signal is present on the respective drc path. the threshold level is configurable (see table 14). 1eh drc1 anti-clip active indicates the drc anti-clip function has been triggered; the drc gain is decreasing in response to a rising signal level. 1fh drc1 decay active indicates that the drc gain is increasing in response to a low-level signal input. 20h drc1 noise gate active indicates t hat the drc noise gate has been triggered; an idle signal condition has been detected. 21h drc1 quick release active indicates that the drc qui ck-release function has been triggered; the drc gain is increasing rapidly following detection of a short transient peak. table 81 dynamic range control (drc) status indications
production data WM5102 w pd, may 2013, rev 4.0 193 control write sequencer status detection gp n _fn = 15h. the WM5102 control write sequencer (wseq) can be us ed to execute a sequence of register write operations in response to a simple trigger even t. see ?control write sequencer? for details of the control write sequencer. the wseq_busy register bit (see table 107) indicates the status of the control write sequencer. when wseq_busy=1, this indicates that one or mo re write sequence operations are in progress or are queued for sequential execution. the write sequencer status may be output directly on any gpio pin by setting the respective gpio registers as described in ?gpio control?. the write sequencer status is an input to the interr upt control circuit. an interrupt event is triggered on completion of a control sequence. the associated interrupt bit is latched once set; it can be polled at any time or used to control the irq signal. see ?i nterrupts? for more details of the interrupt event handling. control interface error status output gp n _fn = 16h. the WM5102 is controlled by writing to registers thr ough a 2-wire serial control interface, as described in the ?control interface? section. the slimbus inte rface also supports read/write access to the control registers, as described in the ?slimbus interface? section. the WM5102 performs automatic checks to confirm if a register access is su ccessful. register access will be unsuccessful if an invalid r egister address is selected. read/wr ite access to the dsp firmware memory will be unsuccessful if the associated clo cking is not enabled. if an invalid or unsuccessful register operation is attempted, this can be indi cated using the gpio and/or interrupt functions. the control interface error signal may be output dire ctly on any gpio pin by setting the respective gpio registers as described in ?gpio control?. the control interface error signal is an input to the interrupt controller circuit. an interrupt event is triggered on the rising edge of the control interface e rror signal. the associated interrupt bit is latched once set; it can be polled at any time or used to control the irq signal. see ?interrupts? for more details of the interrupt event handling. system clocks enable status output gp n _fn = 4bh, 4ch. the WM5102 requires a system clock (sysclk) fo r its internal functions and to support the input/output signal paths. the WM5102 can suppor t two independent clock domains, with selected functions referenced to the asyncclk clock domain. see ?clocking and sample rates? for details of these clocks. the sysclk_ena and async_clk_ena register s (see table 90) control the sysclk and asyncclk signals respectively. when ?0? is written to these registers, the host processor must wait until the WM5102 has shut down the associated functi ons before issuing any other register write commands. the sysclk enable and asyncclk enable status ma y be output directly on any gpio pin by setting the respective gpio register s as described in ?gpio control?. the sysclk enable and asyncclk enable signals are i nputs to the interrupt controller circuit. an interrupt event is triggered when the respective clock functions have been shut down. the associated interrupt bit is latched once set; it can be polled at any time or used to control the irq signal. see ?interrupts? for more details of the interrupt event handling.
WM5102 production data w pd, may 2013, rev 4.0 194 clocking error status output gp n _fn = 0ah, 0bh, 27h, 2dh, 2eh. the WM5102 performs automatic checks to confirm t hat the system clocks are correctly configured according to the commanded functionality. an invalid configuration is one where there are insufficient clock cycles to support the digital proc essing required by the commanded signal paths. an underclocked error condition is where there are insufficient clock cycles for the requested functionality, and increasing the sysclk or asyncclk frequency (as applicable) should allow the selected configuration to be supported. an overclocked error condition is where the requested functiona lity cannot be supported, as the clocking requirements of the requested c onfiguration exceed the device limits. the system clocks (sysclk and, where applicabl e, asyncclk) must be enabled before any signal path is enabled. if an attempt is made to enable a signal path, and there are insufficient clock cycles to support that path, then the attempt will be unsuccessful. note that any signal paths that are already active will not be affected under these circumstances. the clocking error signals may be output directly on any gpio pin by setting the respective gpio registers as described in ?gpio control?. the cl ocking error conditions ar e described in table 82. the clocking error signals are inputs to the interrupt controller circuit. an interrupt event is triggered on the rising and falling edges of the clocking error si gnals. the associated interrupt bits are latched once set; they can be polled at any time or used to control the irq signal. see ?interrupts? for more details of the interrupt event handling. gpn_fn description comments 0ah sysclk underclocked indicates insufficient sysclk cycles for the commanded functionality. 0bh asyncclk underclocked indicates insufficient asyncclk cycles for the commanded functionality. 27h mixer dropped sample error indicates a dropped sample in the digital core mixer function. 2dh underclocked error indicates insufficient sysclk or asyncclk cycles for one or more of the selected signal paths or signal processing functions. increasing the sysclk or asyncclk frequency (as applicable) should allow the selected configuration to be supported. status bits associated with specific sub-systems provide further de-bug capability. the innx_ena_sts bits in register r769 indicate the status of each of the input (analogue or digital microphone) signal paths. the outnx_ena_sts bits in registers r1025 and r1030 indicate the status of each of the output (headphone, speaker or pdm) signal paths. the asrcnx_ena_sts bits in register r3809 indicate the status of each of the asrc signal paths. the fx_sts field in register r3585 indicates the status of each of the effects (eq, drc or lhpf) signal paths. the *mix_stsn fields in registers r1600 to r2920 indicate the status of each of the digital core mixer signal paths. the isrcn and aifn functions are also inputs to the underclocked error status indication, but there are specific _sts register bi ts associated with these. 2eh overclocked error indicates that an unsupported device c onfiguration has been attempted, as the clocking requirements of the requested configuration ex ceed the device limits. table 82 clocking error status indications
production data WM5102 w pd, may 2013, rev 4.0 195 digital audio interface configuration error status output gpn_fn = 28h, 29h, 2ah. the WM5102 performs automatic checks to confirm t hat aif1, aif2 and aif3 are configured with valid settings. invalid settings include conditions where one or more audio channel timeslots are in conflict. if an invalid aif1, aif2 or aif3 configuration is det ected, this can be indica ted using the gpio and/or interrupt functions. the aif configuration error signals may be output dire ctly on any gpio pin by setting the respective gpio registers as described in ?gpio control?. the aif configuration error signals are an input to the interrupt controller circuit. an interrupt event is triggered on the rising and falling edges of the aif conf iguration error signal. the associated interrupt bit is latched once set; it can be polled at any time or used to control the irq signal. see ?interrupts? for more details of the interrupt event handling.
WM5102 production data w pd, may 2013, rev 4.0 196 interrupts the interrupt controller has multiple inputs. t hese include the jack detect and gpio input pins, dsp_irqn flags, headphone / accessory detection, fll / asrc lock detection, and clocking configuration error indications. an y combination of these inputs c an be used to trigger an interrupt request (irq) event. the interrupt controller supports two sets of interr upt registers. this allows two separate interrupt request (irq) outputs to be generated, and for each irq to report a different set of input or status conditions. for each interrupt request (irq1 and irq2) output, there is an interrupt register field associated with each of the interrupt inputs. these fields ar e asserted whenever a logic edge is detected on the respective input. some inputs are triggered on rising edges only; some are triggered on both edges. separate rising and falling interrupt registers are pr ovided for the jd1 and gp5 signals. the interrupt register fields for irq1 are described in table 84. the interrupt register fields for irq2 are described in table 85. the interrupt flags can be polled at any time, or else in response to the interrupt request (irq) output being signalled via the irq pin or a gpio pin. all of the interrupts are edge-triggered, as noted abov e. many of these are triggered on both the rising and falling edges and, therefore, the interrupt registers cannot indicate which edge has been detected. the ?raw status? fields described in t able 86 provide readback of the current value of the corresponding inputs to the interrupt controller. note that the status of any gpio inputs can be read using the gpn_lvl registers, as described in table 76. the underclocked_sts and overclocked_sts register s represent the logical ?or? of status flags from multiple sub-systems. the status bits in registers r3364 to r3367 (see table 86) provide readback of these lower-level signals. see ?clocki ng and sample rates? for a description of the underclocked and overclo cked error conditions. individual mask bits can enable or di sable different functions from t he interrupt controller. the mask bits are described in table 84 (for irq1) and table 85 (for irq2). note that a masked interrupt input will not assert the corresponding interrupt register field, and will not cause the associated interrupt request (irq) output to be asserted. the interrupt request (irq) outputs represent the logi cal ?or? of the associat ed interrupt registers. (irq1 is derived from the _eint1 registers; irq2 is derived from the _eint2 registers). the interrupt register fields are latchi ng fields and, once they are set, they are not reset until a ?1? is written to the respective register bit(s). the interrupt r equest (irq) outputs are not reset until each of the associated interrupts has been reset. a de-bounce circuit can be enabled on any gpio input, to avoid false event triggers. this is enabled on each pin using the register bits described in table 76. the irq outputs can be globally masked using the im_irq1 and im_irq2 register bits. when not masked, the irq status can be read from irq1_sts and irq2_sts for the respective irq outputs. the irq1 output is provided externally on the irq pin. under default conditi ons, this output is ?active low?. the polarity can be inverted using the irq_pol register. the irq output can be either cmos driven or open drain; this is sele cted using the irq_op_cfg register. the irq1 and irq2 signals may be output on a gpio pin - see ?general purpose input / output?. the WM5102 interrupt controller circuit is illustrated in figure 63. (note that not all interrupt inputs are shown.) the associated control fields are described in table 83 to table 86. note that, under default register conditions, the ?b oot done? status is the only un-masked interrupt source; a falling edge on the irq pin will indicate completion of the boot sequence.
production data WM5102 w pd, may 2013, rev 4.0 197 figure 63 interrupt controller register address bit label default description r3087 (0c0fh) irq ctrl 1 10 irq_pol 1 irq output polarity select 0 = non-inverted (active high) 1 = inverted (active low) 9 irq_op_cfg 0 irq output configuration 0 = cmos 1 = open drain table 83 irq output control registers
WM5102 production data w pd, may 2013, rev 4.0 198 register address bit label default description r3328 (0d00h) interrupt status 1 3 gp4_eint1 0 gpio4 interrupt (rising and falling edge triggered) note: cleared when a ?1? is written. 2 gp3_eint1 0 gpio3 interrupt (rising and falling edge triggered) note: cleared when a ?1? is written. 1 gp2_eint1 0 gpio2 interrupt (rising and falling edge triggered) note: cleared when a ?1? is written. 0 gp1_eint1 0 gpio1 interrupt (rising and falling edge triggered) note: cleared when a ?1? is written. r3329 (0d01h) interrupt status 2 8 dsp1_ram_rdy _eint1 0 dsp1 ram ready interrupt (rising edge triggered) note: cleared when a ?1? is written. 1 dsp_irq2_eint 1 0 dsp irq2 interrupt (rising and falling edge triggered) note: cleared when a ?1? is written. 0 dsp_irq1_eint 1 0 dsp irq1 interrupt (rising and falling edge triggered) note: cleared when a ?1? is written. r3330 (0d02h) interrupt status 3 15 spk_shutdow n_warn_eint1 0 speaker shutdown warning interrupt (rising and falling edge triggered) note: cleared when a ?1? is written. 14 spk_shutdow n_eint1 0 speaker shutdown interrupt (rising and falling edge triggered) note: cleared when a ?1? is written. 13 hpdet_eint1 0 headphone detect interrupt (rising edge triggered) note: cleared when a ?1? is written. 12 micdet_eint1 0 microphone / accessory detect interrupt (detection event triggered) note: cleared when a ?1? is written. 11 wseq_done_ei nt1 0 write sequencer done interrupt (rising edge triggered) note: cleared when a ?1? is written. 9 drc1_sig_det _eint1 0 drc1 signal detect interrupt (rising and falling edge triggered) note: cleared when a ?1? is written. 8 asrc2_lock_e int1 0 asrc2 lock interrupt (rising and falling edge triggered) note: cleared when a ?1? is written. 7 asrc1_lock_e int1 0 asrc1 lock interrupt (rising and falling edge triggered) note: cleared when a ?1? is written. 6 underclocke d_eint1 0 underclocked error interrupt (rising edge triggered) note: cleared when a ?1? is written. 5 overclocked _eint1 0 overclocked error interrupt (rising edge triggered) note: cleared when a ?1? is written.
production data WM5102 w pd, may 2013, rev 4.0 199 register address bit label default description 3 fll2_lock_ein t1 0 fll2 lock interrupt (rising and falling edge triggered) note: cleared when a ?1? is written. 2 fll1_lock_ein t1 0 fll1 lock interrupt (rising and falling edge triggered) note: cleared when a ?1? is written. 1 clkgen_err_e int1 0 sysclk underclocked error interrupt (rising edge triggered) note: cleared when a ?1? is written. 0 clkgen_err_a sync_eint1 0 asyncclk underclocked error interrupt (rising edge triggered) note: cleared when a ?1? is written. r3331 (0d03h) interrupt status 4 15 asrc_cfg_er r_eint1 0 asrc configuration error interrupt (rising edge triggered) note: cleared when a ?1? is written. 14 aif3_err_eint 1 0 aif3 configuration error interrupt (rising edge triggered) note: cleared when a ?1? is written. 13 aif2_err_eint 1 0 aif2 configuration error interrupt (rising edge triggered) note: cleared when a ?1? is written. 12 aif1_err_eint 1 0 aif1 configuration error interrupt (rising edge triggered) note: cleared when a ?1? is written. 11 ctrlif_err_ei nt1 0 control interface error interrupt (rising edge triggered) note: cleared when a ?1? is written. 10 mixer_droppe d_sample_ein t1 0 mixer dropped sample interrupt (rising edge triggered) note: cleared when a ?1? is written. 9 async_clk_en a_low_eint1 0 async_clk_ena interrupt (triggered on asyncclk shut-down) note: cleared when a ?1? is written. 8 sysclk_ena_l ow_eint1 0 sysclk_ena interrupt (triggered on sysclk shut-down) note: cleared when a ?1? is written. 7 isrc1_cfg_er r_eint1 0 isrc1 configuration error interrupt (rising edge triggered) note: cleared when a ?1? is written. 6 isrc2_cfg_er r_eint1 0 isrc2 configuration error interrupt (rising edge triggered) note: cleared when a ?1? is written. r3332 (0d04h) interrupt status 5 8 boot_done_ei nt1 0 boot done interrupt (rising edge triggered) note: cleared when a ?1? is written. 7 dcs_dac_don e_eint1 0 dc servo dac interrupt (rising edge triggered) note: cleared when a ?1? is written. 6 dcs_hp_done_ eint1 0 dc servo hpout interrupt (rising edge triggered) note: cleared when a ?1? is written.
WM5102 production data w pd, may 2013, rev 4.0 200 register address bit label default description 1 fll2_clock_o k_eint1 0 fll2 clock ok interrupt (rising and falling edge triggered) note: cleared when a ?1? is written. 0 fll1_clock_o k_eint1 0 fll1 clock ok interrupt (rising and falling edge triggered) note: cleared when a ?1? is written. r3336 (0d08h) to r3340 (0d0ch) im_* (see note) for each *_eint1 interrupt register in r3328 to r3332, a corresponding mask bit (im_*) is provided in r3336 to r3340. the mask bits are coded as: 0 = do not mask interrupt 1 = mask interrupt note : the boot_done_eint1 interrupt is ?0? (un-masked) by default; all other interrupts are ?1? (masked) by default. r3343 (0d0fh) interrupt control 0 im_irq1 0 irq1 output interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. r3409 (0d51h) aod irq1 7 micd_clamp_f all_eint1 0 micdet clamp interrupt (falling edge triggered) note: cleared when a ?1? is written. 6 micd_clamp_r ise_eint1 0 micdet clamp interrupt (rising edge triggered) note: cleared when a ?1? is written. 5 gp5_fall_eint 1 0 gp5 interrupt (falling edge triggered) note: cleared when a ?1? is written. 4 gp5_rise_eint 1 0 gp5 interrupt (rising edge triggered) note: cleared when a ?1? is written. 3 jd1_fall_eint 1 0 jd1 interrupt (falling edge triggered) note: cleared when a ?1? is written. 2 jd1_rise_eint1 0 jd1 interrupt (rising edge triggered) note: cleared when a ?1? is written. r3411 (0d53h) aod irq mask irq1 im_* 1 for each *_eint1 interrupt register in r3409, a corresponding mask bit (im_*) is provided in r3411. the mask bits are coded as: 0 = do not mask interrupt 1 = mask interrupt table 84 interrupt 1 control registers register address bit label default description r3344 (0d10h) irq2 status 1 3 gp4_eint2 0 gpio4 interrupt (rising and falling edge triggered) note: cleared when a ?1? is written. 2 gp3_eint2 0 gpio3 interrupt (rising and falling edge triggered) note: cleared when a ?1? is written.
production data WM5102 w pd, may 2013, rev 4.0 201 register address bit label default description 1 gp2_eint2 0 gpio2 interrupt (rising and falling edge triggered) note: cleared when a ?1? is written. 0 gp1_eint2 0 gpio1 interrupt (rising and falling edge triggered) note: cleared when a ?1? is written. r3345 (0d11h) irq2 status 2 8 dsp1_ram_rdy _eint2 0 dsp1 ram ready interrupt (rising edge triggered) note: cleared when a ?1? is written. 1 dsp_irq2_eint 2 0 dsp irq2 interrupt (rising and falling edge triggered) note: cleared when a ?1? is written. 0 dsp_irq1_eint 2 0 dsp irq1 interrupt (rising and falling edge triggered) note: cleared when a ?1? is written. r3346 (0d12h) irq2 status 3 15 spk_shutdow n_warn_eint2 0 speaker shutdown warning interrupt (rising and falling edge triggered) note: cleared when a ?1? is written. 14 spk_shutdow n_eint2 0 speaker shutdown interrupt (rising and falling edge triggered) note: cleared when a ?1? is written. 13 hpdet_eint2 0 headphone detect interrupt (rising edge triggered) note: cleared when a ?1? is written. 12 micdet_eint2 0 microphone / accessory detect interrupt (detection event triggered) note: cleared when a ?1? is written. 11 wseq_done_ei nt2 0 write sequencer done interrupt (rising edge triggered) note: cleared when a ?1? is written. 9 drc1_sig_det _eint2 0 drc1 signal detect interrupt (rising and falling edge triggered) note: cleared when a ?1? is written. 8 asrc2_lock_e int2 0 asrc2 lock interrupt (rising and falling edge triggered) note: cleared when a ?1? is written. 7 asrc1_lock_e int2 0 asrc1 lock interrupt (rising and falling edge triggered) note: cleared when a ?1? is written. 6 underclocke d_eint2 0 underclocked error interrupt (rising edge triggered) note: cleared when a ?1? is written. 5 overclocked _eint2 0 overclocked error interrupt (rising edge triggered) note: cleared when a ?1? is written. 3 fll2_lock_ein t2 0 fll2 lock interrupt (rising and falling edge triggered) note: cleared when a ?1? is written. 2 fll1_lock_ein t2 0 fll1 lock interrupt (rising and falling edge triggered) note: cleared when a ?1? is written.
WM5102 production data w pd, may 2013, rev 4.0 202 register address bit label default description 1 clkgen_err_e int2 0 sysclk underclocked error interrupt (rising edge triggered) note: cleared when a ?1? is written. 0 clkgen_err_a sync_eint2 0 asyncclk underclocked error interrupt (rising edge triggered) note: cleared when a ?1? is written. r3347 (0d13h) irq2 status 4 15 asrc_cfg_er r_eint2 0 asrc configuration error interrupt (rising edge triggered) note: cleared when a ?1? is written. 14 aif3_err_eint 2 0 aif3 configuration error interrupt (rising edge triggered) note: cleared when a ?1? is written. 13 aif2_err_eint 2 0 aif2 configuration error interrupt (rising edge triggered) note: cleared when a ?1? is written. 12 aif1_err_eint 2 0 aif1 configuration error interrupt (rising edge triggered) note: cleared when a ?1? is written. 11 ctrlif_err_ei nt2 0 control interface error interrupt (rising edge triggered) note: cleared when a ?1? is written. 10 mixer_droppe d_sample_ein t2 mixer dropped sample interrupt (rising edge triggered) note: cleared when a ?1? is written. 9 async_clk_en a_low_eint2 0 async_clk_ena interrupt (triggered on asyncclk shut-down) note: cleared when a ?1? is written. 8 sysclk_ena_l ow_eint2 0 sysclk_ena interrupt (triggered on sysclk shut-down) note: cleared when a ?1? is written. 7 isrc1_cfg_er r_eint2 0 isrc1 configuration error interrupt (rising edge triggered) note: cleared when a ?1? is written. 6 isrc2_cfg_er r_eint2 0 isrc2 configuration error interrupt (rising edge triggered) note: cleared when a ?1? is written. r3348 (0d14h) irq2 status 5 8 boot_done_ei nt2 0 boot done interrupt (rising edge triggered) note: cleared when a ?1? is written. 7 dcs_dac_don e_eint2 0 dc servo dac interrupt (rising edge triggered) note: cleared when a ?1? is written. 6 dcs_hp_done_ eint2 0 dc servo hpout interrupt (rising edge triggered) note: cleared when a ?1? is written. 1 fll2_clock_o k_eint2 0 fll2 clock ok interrupt (rising and falling edge triggered) note: cleared when a ?1? is written. 0 fll1_clock_o k_eint2 0 fll1 clock ok interrupt (rising and falling edge triggered) note: cleared when a ?1? is written.
production data WM5102 w pd, may 2013, rev 4.0 203 register address bit label default description r3352 (0d18h) to r3356 (0d1ch) im_* (see note) for each *_eint2 interrupt register in r3344 to r3348, a corresponding mask bit (im_*) is provided in r3352 to r3356. the mask bits are coded as: 0 = do not mask interrupt 1 = mask interrupt note : the boot_done_eint2 interrupt is ?0? (un-masked) by default; all other interrupts are ?1? (masked) by default. r3359 (0d1fh) irq2 control 0 im_irq2 0 irq2 output interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. r3410 (0d52h) aod irq2 7 micd_clamp_f all_eint2 0 micdet clamp interrupt (falling edge triggered) note: cleared when a ?1? is written. 6 micd_clamp_r ise_eint2 0 micdet clamp interrupt (rising edge triggered) note: cleared when a ?1? is written. 5 gp5_fall_eint 2 0 gp5 interrupt (falling edge triggered) note: cleared when a ?1? is written. 4 gp5_rise_eint 2 0 gp5 interrupt (rising edge triggered) note: cleared when a ?1? is written. 3 jd1_fall_eint 2 0 jd1 interrupt (falling edge triggered) note: cleared when a ?1? is written. 2 jd1_rise_eint2 0 jd1 interrupt (rising edge triggered) note: cleared when a ?1? is written. r3412 (0d54h) aod irq mask irq2 im_* 1 for each *_eint2 interrupt register in r3410, a corresponding mask bit (im_*) is provided in r3412. the mask bits are coded as: 0 = do not mask interrupt 1 = mask interrupt table 85 interrupt 2 control registers register address bit label default description r3360 (0d20h) interrupt raw status 2 8 dsp1_ram_rdy _sts 0 dsp1 ram status 0 = not ready 1 = ready 1 dsp_irq2_sts 0 dsp irq2 status 0 = not asserted 1 = asserted 0 dsp_irq1_sts 0 dsp irq1 status 0 = not asserted 1 = asserted r3361 (0d21h) interrupt 15 spk_shutdow n_warn_sts 0 speaker shutdown warning status 0 = normal 1 = warning temperature exceeded
WM5102 production data w pd, may 2013, rev 4.0 204 register address bit label default description raw status 2 14 spk_shutdow n_sts 0 speaker shutdown status 0 = normal 1 = shutdown temperature exceeded 11 wseq_done_s ts 0 write sequencer status 0 = busy (sequence in progress) 1 = idle (sequence completed) 9 drc1_sig_det _sts 0 drc1 signal detect status 0 = normal 1 = signal detected 8 asrc2_lock_s ts 0 asrc2 lock status 0 = not locked 1 = locked 7 asrc1_lock_s ts 0 asrc1 lock status 0 = not locked 1 = locked 6 underclocke d_sts 0 underclocked error status 0 = normal 1 = underclocked error 5 overclocked _sts 0 overclocked error status 0 = normal 1 = overclocked error 3 fll2_lock_sts 0 fll2 lock status 0 = not locked 1 = locked 2 fll1_lock_sts 0 fll1 lock status 0 = not locked 1 = locked 1 clkgen_err_s ts 0 sysclk underclocked error status 0 = normal 1 = underclocked error 0 clkgen_err_a sync_sts 0 asyncclk underclocked error status 0 = normal 1 = underclocked error r3362 (0d22h) interrupt raw status 4 15 asrc_cfg_er r_sts 0 asrc configuration error interrupt 0 = normal 1 = configuration error 14 aif3_err_sts 0 aif3 configuration error status 0 = normal 1 = configuration error 13 aif2_err_sts 0 aif2 configuration error status 0 = normal 1 = configuration error 12 aif1_err_sts 0 aif1 configuration error status 0 = normal 1 = configuration error 11 ctrlif_err_st s 0 control interface error status 0 = normal 1 = control interface error 10 mixer_droppe d_sample_sts mixer dropped sample status 0 = normal 1 = dropped sample error
production data WM5102 w pd, may 2013, rev 4.0 205 register address bit label default description 9 async_clk_en a_low_sts 0 async_clk_ena status 0 = async_clk_ena is enabled 1 = async_clk_ena is disabled when a ?0? is written to asyncclk_ena, then no other control register writes should be attempted until async_clk_ena_low_sts=1. 8 sysclk_ena_l ow_sts 0 sysclk_ena status 0 = sysclk_ena is enabled 1 = sysclk_ena is disabled when a ?0? is written to sysclk_ena, then no other control register writes should be attempted until sysclk_ena_low_sts=1. 7 isrc1_cfg_er r_sts 0 isrc1 configuration error interrupt 0 = normal 1 = configuration error 6 isrc2_cfg_er r_sts 0 isrc2 configuration error interrupt 0 = normal 1 = configuration error r3363 (0d23h) interrupt raw status 5 8 boot_done_s ts 0 boot status 0 = busy (boot sequence in progress) 1 = idle (boot sequence completed) control register writes should not be attempted until boot sequence has completed. 7 dcs_dac_don e_sts 0 dc servo dac status 0 = busy (dc servo in progress) 1 = idle (dc servo completed) 6 dsc_hp_done_ sts 0 dc servo hpout status 0 = busy (dc servo in progress) 1 = idle (dc servo completed) 1 fll2_clock_o k_sts 0 fll2 clock ok interrupt 0 = fll2 clock is not ok 1 = fll2 clock is ok 0 fll1_clock_o k_sts 0 fll1 clock ok interrupt 0 = fll1 clock is not ok 1 = fll1 clock is ok r3364 (0d24h) interrupt raw status 6 13 pwm_overclo cked_sts 0 indicates an overclocked error condition for each respective sub-system. the bits are coded as: 0 = normal 1 = overclocked the overclocked_sts bit will be asserted whenever any of these register bits is asserted. 12 fx_core_ove rclocked_sts 0 10 dac_sys_over clocked_sts 0 9 dac_warp_ov erclocked_st s 0 8 adc_overclo cked_sts 0 7 mixer_overcl ocked_sts 0 6 aif3_async_o verclocked_ sts 0
WM5102 production data w pd, may 2013, rev 4.0 206 register address bit label default description 5 aif2_async_o verclocked_ sts 0 4 aif1_async_o verclocked_ sts 0 3 aif3_sync_ov erclocked_st s 0 2 aif2_sync_ov erclocked_st s 0 1 aif1_sync_ov erclocked_st s 0 0 pad_ctrl_ove rclocked_sts 0 r3365 (0d25h) interrupt raw status 7 15 slimbus_subs ys_overcloc ked_sts 0 indicates an overclocked error condition for each respective sub-system. the bits are coded as: 0 = normal 1 = overclocked the overclocked_sts bit will be asserted whenever any of these register bits is asserted. 14 slimbus_asyn c_overclock ed_sts 0 13 slimbus_sync _overclocke d_sts 0 12 asrc_async_s ys_overcloc ked_sts 0 11 asrc_async_ warp_overcl ocked_sts 0 10 asrc_sync_sy s_overclock ed_sts 0 9 asrc_sync_w arp_overclo cked_sts 0 3 dsp1_overclo cked_sts 0 1 isrc2_overcl ocked_sts 0 0 isrc1_overcl ocked_sts 0 r3366 (0d26h) interrupt raw status 8 10 aif3_undercl ocked_sts 0 indicates an underclocked error condition for each respective sub- system. the bits are coded as: 0 = normal 1 = overclocked the underclocked_sts bit will be asserted whenever any of these register bits is asserted. 9 aif2_undercl ocked_sts 0 8 aif1_undercl ocked_sts 0 6 isrc2_underc locked_sts 0 5 isrc1_underc locked_sts 0 4 fx_underclo cked_sts 0 3 asrc_underc locked_sts 0
production data WM5102 w pd, may 2013, rev 4.0 207 register address bit label default description 2 dac_undercl ocked_sts 0 1 adc_undercl ocked_sts 0 0 mixer_underc locked_sts 0 r3392 (0d40h) interrupt pin status 1 irq2_sts 0 irq2 status irq2_sts is the logical ?or? of all unmasked _eint2 interrupts. 0 = not asserted 1 = asserted 0 irq1_sts 0 irq1 status irq1_sts is the logical ?or? of all unmasked _eint1 interrupts. 0 = not asserted 1 = asserted r3413 (0d55h) aod irq raw status 3 micd_clamp_s ts 0 micdet clamp status 0 = clamp not active 1 = clamp active note that the micdet clamp is provided on the micdet1 or micdet2 pins, depending on the accdet_src register bit. 2 gp5_sts 0 gp5 status 0 = not asserted 1 = asserted 0 jd1_sts 0 jackdet input status 0 = jack not detected 1 = jack is detected (assumes the jackdet pin is pulled ?low? on jack insertion.) table 86 interrupt status
WM5102 production data w pd, may 2013, rev 4.0 208 clocking and sample rates the WM5102 requires a clock reference for its inter nal functions and also fo r the input (adc) paths, output (dac) paths and digital audio interfaces. under typical clocking configurations, all commonly- used audio sample rates can be derived directly from the external reference; for additional flexibility, the WM5102 incorporates two frequency locked loop (f ll) circuits to perfo rm frequency conversion and filtering. external clock signals may be connected via mclk 1 and mclk2. (note that mclk1 and mclk2 are referenced to the dbvdd1 and dbvdd2 power domains respectively.) in aif slave modes, the bclk signals may be used as a reference for the system clocks. the slimbus interface can provide the clock reference, when used as the input to one of the flls. to avoid audible glitches, all clock configurations must be set up before enabling playback. system clocking the WM5102 supports two independent clock domains , referenced to the sysclk and asyncclk system clocks respectively. up to five different sample rates may be independently selected for specific audio interfaces and other input/output signal paths. each selected sample rate must be synchronised either to sysclk or to asyncclk, as described later. the two system clocks are independent (ie. not sy nchronised). stereo full-duplex sample rate conversion is supported, allowing asynchronous audio data to be mixed and to be routed between independent interfaces. see ?digital core? for further details. each subsystem within the WM5102 digital core is clocked at a dynamically-controlled rate, limited by the sysclk (or asyncclk) frequency, as applicabl e. for maximum signal mixing and processing capacity, it is recommended that the highes t possible sysclk and asyncclk frequencies are configured. if the subsys_max_freq bit is set to ?0?, then t he digital core clocking rate is restricted to a maximum of 24.576mhz (or 22.5792mhz), even if a higher system clock frequency is configured. the maximum digital core clocking rates of 49.152mhz (or 45.1584mhz) are only supported when subsys_max_freq is set to ?1?, and the dcvdd voltage is 1.8v (nominal). see ?recommended operating conditions? for details of the dcvdd operating conditions. note that, if dcvdd is less than the minimum level for > 24.576mhz clocking, then subsys_max_freq must be set to ?0?. register address bit label default description r353 (0161h) dynamic frequency scaling 1 0 subsys_max_f req 0 digital core clocking limit sets the maximum digital core clocking rate. the higher rate should only be selected when the dcvdd voltage is 1.8v (nominal). 0 = 24.576mhz (22.5792mhz) 1 = 49.152mhz (45.1584mhz) table 87 system clocking sample rate control the WM5102 supports two independent clock domai ns, referenced to sysclk and asyncclk respectively. different sample rates may be selected for each of the audio interfaces (aif1, aif2, aif3, slimbus), and for the input (adc) and output (dac) paths. each of these must be referenced either to sysclk or to asyncclk. (note that the slimbus interface supports multiple sample rates, selected independently for each input or output channel.) the WM5102 can support a maximum of five differ ent sample rates at any time. the supported
production data WM5102 w pd, may 2013, rev 4.0 209 sample rates range from 4khz to 192khz. up to three different sample rates can be selected using the sample_rate_1, sample_rate_2 and sample_rate_3 registers. these must each be numerically related to each other and to the sysclk frequency (further details of these requirements are provided in table 88 and the accompanying text). the remaining two sample rates can be selected using the async_sample_rate_1 and async_sample_rate_2 registers. these sample rate s must be numerically related to each other and to the asyncclk frequency (further details of these requirements are provided in table 89 and the accompanying text). each of the audio interfaces, input paths and output paths is associated with one of the sample rates selected by the sample_rate_n or async_sample_rate_n registers. note that if any two interfaces are operating at the same sample rate, but are not synchronised, then one of these must be referenced to the asynclk domain, and the other to the sysclk domain. note that, when any of the sample_rate_n or async_sample_rate_n registers is written to, the activation of the new setting is automatically synchronised by the WM5102 to ensure continuity of all active signal paths. the sample_rate _n_sts and async_sample_rate_n_sts registers provide readback of the sample rate selections that have been implemented. there are some restrictions to be observed regarding the sample rate control configuration, as noted below: ? the input (adc / digital microphone) and out put (dac) signal paths must always be associated with the sysclk clocking domain. ? all external clock references (mclk input or slave mode aif input) must be within 1% of the applicable register setting(s). ? the input (adc / dmic) sample rate is valid from 8khz to 192khz. ? the output (dac) sample rate is valid from 8khz to 96khz. ? the mic mute mixer sample rate is valid from 8khz to 192khz. ? the effects (eq, drc, lhpf) sample rate is valid from 8khz to 192khz. ? the tone generator sample rate is valid from 8khz to 192khz. ? the haptic signal generator sample rate is valid from 8khz to 192khz. ? the asynchronous sample rate converter (as rc) supports sample rates 8khz to 48khz. the associated sysclk and asynclk sample rates must both be 8khz to 48khz. ? the isochronous sample rate converters (i srcs) support sample rates 8khz to 192khz. for each isrc, the higher sample rate must be an integer multiple of the lower rate. integer ratios in the range 1 to 6 are supported. automatic sample rate detection the WM5102 supports automatic sample rate detection on the digital audio interfaces (aif1, aif2 and aif3). note that this is only possible when the re spective interface is oper ating in slave mode (ie. when lrclk and bclk are inputs to the WM5102). automatic sample rate detection is enabled using t he rate_est_ena register bit. the lrclk input pin selected for sample rate detection is set using the lrclk_src register. up to four audio sample rates can be configured for automatic detection; these sample rates are selected using the sample_rate_detect_n registers. note that the function will only detect sample rates that match one of the sample_rate_detect_n registers. if one of the selected audio sample rates is detected on the selected lrclk input, then a control write sequence will be triggered. a unique sequence of actions may be programmed for each of the detected sample rates. note that the applicable control sequences must be programmed by the user for each detection outcome. see ?control write sequencer? for further details.
WM5102 production data w pd, may 2013, rev 4.0 210 the trig_on_startup register cont rols whether the sample rate detection circuit responds to the initial detection of the applicable interface (ie. when the aifn interface starts up). when trig_on_startup=0, then the detection circ uit will only respond (ie. trigger the control write sequencer) to a change in the detected sample rate - the initial sample rate detection will be ignored. (note that the ?initial sample rate detection? is the first detection of a sample rate that matches one of the sample_rate_detect_n registers.) when trig_on_startup=1, then the detection circ uit will trigger the control write sequencer whenever a selected sample rate is detected, incl uding when the aif interface starts up, or when the sample rate detection is first enabled. there are some restrictions to be observed regarding the sample rate control configuration, as noted below: ? the same sample rate must not be selected on more than one of the sample_rate_detect_n registers. ? sample rates 192khz and 176.4khz must not be selected concurrently. ? sample rates 96khz and 88.2khz must not be selected concurrently. the control registers associated with the automatic sample rate detection function are described in table 90. sysclk and asyncclk control the sysclk and asyncclk clocks may be provided direct ly from external inputs (mclk, or slave mode bclk inputs). alternatively, the sysc lk and asyncclk clocks can be derived using the integrated fll(s), with mclk, bclk, lrclk or slimclk as a reference. the required sysclk frequency is dependent on the sample_rate_n registers. table 88 illustrates the valid sysclk frequencie s for every supported sample rate. the sysclk_freq and sysclk_frac registers are used to identify the applicable sysclk frequency. it is recommended that the highest possible sysclk frequency is selected. the chosen sysclk frequency must be valid for all of the sample_rate_n registers. it follows that all of the sample_rate_n registers must select numer ically-related values, ie. all from the same cell as represented in table 88. sample rate sample_rate_n sysclk frequency sysclk_freq sysclk_frac 12khz 24khz 48khz 96khz 192khz 4khz 8khz 16khz 32khz 01h 02h 03h 04h 05h 10h 11h 12h 13h 6.144mhz, 12.288mhz, 24.576mhz, or 49.152mhz 000, 001, 010, or 011 0 11.025khz 22.05khz 44.1khz 88.2khz 176.4khz 09h 0ah 0bh 0ch 0dh 5.6448mhz, 11.2896mhz, 22.5792mhz, or 45.1584mhz 000, 001, 010, or 011 1 note that each of the sample_rate_n registers must select a sample rate value from the same group in the two lists above. table 88 sysclk frequency selection
production data WM5102 w pd, may 2013, rev 4.0 211 the required asyncclk frequency is dependent on t he async_sample_rate_n registers. table 89 illustrates the valid asyncclk frequencies for every supported sample rate. the async_clk_freq register is used to identify the applicable asyncclk frequency. it is recommended that the highest possible asyncclk frequency is selected. note that, if all the sample rates in the sy stem are synchronised to sysclk, then the asyncclk may not be required at all. in this case, t he asyncclk should be disabl ed (see table 90), and the associated register values are not important. sample rate async_sample_rate_n asyncclk frequency async_clk_freq 12khz 24khz 48khz 96khz 192khz 4khz 8khz 16khz 32khz 01h 02h 03h 04h 05h 10h 11h 12h 13h 6.144mhz, 12.288mhz, 24.576mhz, or 49.152mhz 000, 001, 010, or 011 11.025khz 22.05khz 44.1khz 88.2khz 176.4khz 09h 0ah 0bh 0ch 0dh 5.6448mhz, 11.2896mhz, 22.5792mhz or 45.1584mhz 000, 001, 010, or 011 note that each of the async_sample_rate_n regist ers must select a sample rate value from the same group in the two lists above. table 89 asyncclk frequency selection the WM5102 supports automatic clocking configurati on. the programmable dividers associated with the adcs, dacs and all dsp functi ons are configured automatically, with values determined from the sysclk_freq, sample_rate_n, async_clk_freq and async_sample_rate_n fields. note that the digital audio interface (aif) clocking rates must be configured separately. the sample rates of each aif, the input (adc) paths, output (dac) paths and dsp functions are selected as described in the respective sections . stereo full-duplex sample rate conversion is supported in multiple configurations to allow digital audio to be routed between interfaces and for asynchronous audio data to be mixed. see ?digital core? for further details. the sysclk_src register is used to select the sysclk source, as described in table 90. the source may be mclkn, aifnbclk or flln. if one of the frequency locked loop (fll) circuits is selected as the source, then the relevant fll must be enabled and configured, as described later. the sysclk_freq and sysclk_frac registers are set according to the frequency of the selected sysclk source. the sysclk-referenced circuits within the digital core are clocked at a dynamically-controlled rate, limited by the sysclk frequency itself. for maximu m signal mixing and processing capacity, it is recommended that the highest possible sysclk frequency is configured. if the subsys_max_freq bit is set to ?0?, then t he digital core clocking rate is restricted to a maximum of 24.576mhz (or 22.5792mhz), even if a higher sysclk frequency is configured. the subsys_max_freq should only be set to ?1? when the applicable dcvdd conditi on is satisfied, as described in table 87. the sample_rate_n registers are set according to the sample rate(s) that are required by one or more of the WM5102 audio interfaces. the WM5102 s upports sample rates ranging from 4khz to 192khz.
WM5102 production data w pd, may 2013, rev 4.0 212 the sysclk signal is enabled by the register bit sysclk_ena. the applicable clock source (mclkn, aifnbclk or flln) must be enabled befor e setting sysclk_ena=1. this bit should be set to 0 when reconfiguring the clock sources (s ee below for additional requirements when setting sysclk_ena=0). when disabling sysclk, note that all of the input, out put or digital core functions associated with the sysclk clock domain must be disabled before setting sysclk_ena=0. when ?0? is written to sysclk_ena, the host pr ocessor must wait until the WM5102 has shut down the associated functions before issuing any other register write commands. the sysclk enable status can be polled via the sysclk_ena_low_sts bi t (see table 86), or else monitored using the interrupt or gpio functions. the sysclk enable status is an input to the inte rrupt control circuit and can be used to trigger an interrupt event - see ?interrupts?. the correspondi ng interrupt event indicates that the WM5102 has shut down the sysclk functions and is r eady to accept register write commands. the sysclk enable status can be output directly on a gpio pin as an external indication of the sysclk status. see ?general purpose input / output ? to configure a gpio pin for this function. the required control sequence for dis abling sysclk is summarised below: ? disable all sysclk-associated functi ons (inputs, outputs, digital core) ? set sysclk_ena = 0 ? wait until sysclk_ena_low = 1 (or wait for the corresponding irq/gpio event) the async_clk_src register is used to select the asyncclk source, as described in table 90. the source may be mclkn, aifnbclk or flln. if one of the frequency locked loop (fll) circuits is selected as the source, then the relevant fll must be enabled and configured, as described later. the async_clk_freq register is set accord ing to the frequency of the selected asyncclk source. the asyncclk-referenced circuits wi thin the digital core are clocked at a dynamically-controlled rate, limited by the asyncclk frequency itself. for maximum signal mixing and processing capacity, it is recommended that the highest po ssible asyncclk frequency is configured. if the subsys_max_freq bit is set to ?0?, then t he digital core clocking rate is restricted to a maximum of 24.576mhz (or 22.5792mhz), even if a higher asyncclk frequency is configured. the subsys_max_freq should only be set to ?1? when the applicable dcvdd conditi on is satisfied, as described in table 87. the async_sample_rate_n registers are set according to the sample rate(s) of any audio interface that is not synchronised to the sysclk clock domain. the asyncclk signal is enabled by the register bi t async_clk_ena. the applicable clock source (mclkn, aifnbclk or flln) must be enabled before setting async_clk_ena=1. this bit should be set to 0 when reconfiguring the clock source s (see below for additional requirements when setting async_clk_ena=0). when disabling asyncclk, note that all of the input, output or digital core functions associated with the asyncclk clock domain must be disabled before setting async_clk_ena=0. when ?0? is written to async_clk_ena, the host processor must wait until the WM5102 has shut down the associated functions before issuing any other register write commands. the asyncclk enable status can be polled via the async_clk_ ena_low_sts bit (see table 86), or else monitored using the interr upt or gpio functions. the asnycclk enable status is an input to the inte rrupt control circuit and can be used to trigger an interrupt event - see ?interrupts?. the correspondi ng interrupt event indicates that the WM5102 has shut down the asyncclk functions and is ready to accept register write commands. the asnycclk enable status can be output directly on a gpio pin as an exte rnal indication of the asnycclk status. see ?general purpose input / output ? to configure a gpio pin for this function.
production data WM5102 w pd, may 2013, rev 4.0 213 the required control sequence for dis abling asyncclk is summarised below: ? disable all asyncclk-associated functi ons (inputs, outputs, digital core) ? set asyncclk_ena = 0 ? wait until asyncclk_ena_low = 1 (or wait for the corresponding irq/gpio event) the sysclk (and asyncclk, when applicable) clocks must be configured and enabled before any audio path is enabled. the WM5102 performs automatic checks to conf irm that the sysclk and asyncclk frequencies are high enough to support the commanded signal paths and processing functions. if an attempt is made to enable a signal path or processing func tion, and there are insufficient sysclk or asyncclk cycles to support it, then the attempt will be unsuccessful. (note that any signal paths that are already active will not be a ffected under these circumstances.) an underclocked error condition is where there are insufficient clock cycles for the requested functionality, and increasing the sysclk or asyncclk frequency (as applicable) should allow the selected configuration to be supported. an overclocked error condition is where the requested functiona lity cannot be supported, as the clocking requirements of the requested c onfiguration exceed the device limits. the sysclk underclocked condition, asyncclk u nderclocked condition, and other clocking error conditions can be monitor ed using the gpio and/or interrupt f unctions. see ?general purpose input / output? and ?interrupts? for further details. miscellaneous clock controls the WM5102 requires a 32khz clock for miscell aneous de-bounce functions. this can be generated automatically from sysclk, or may be input directly as mclk1 or mclk2. the 32khz clock source is selected using the clk_32k_src register. the 32khz clock is enabled using the clk_32k_ena register. a clock output (opclk) derived from sysclk can be output on a gpio pin. see ?general purpose input / output? to configure a gpio pin for this function. a clock output (opclk_async) derived from asyncclk can be output on a gpio pin. see ?general purpose input / output? to conf igure a gpio pin for this function. the WM5102 provides integrated pull-down resistors on the mclk1 and mclk2 pins. this provides a flexible capability for interfacing with other devices. the clocking scheme for the WM5102 is illustrated in figure 64.
WM5102 production data w pd, may 2013, rev 4.0 214 figure 64 system clocking
production data WM5102 w pd, may 2013, rev 4.0 215 the WM5102 clocking control regist ers are described in table 90. register address bit label default description r256 (0100h) clock 32k 1 6 clk_32k_ena 0 32khz clock enable 0 = disabled 1 = enabled 1:0 clk_32k_src [1:0] 10 32khz clock source 00 = mclk1 (direct) 01 = mclk2 (direct) 10 = sysclk (automatically divided) 11 = reserved r257 (0101h) system clock 1 15 sysclk_frac 0 sysclk frequency 0 = sysclk is a multiple of 6.144mhz 1 = sysclk is a multiple of 5.6448mhz 10:8 sysclk_freq [2:0] 011 sysclk frequency 000 = 6.144mhz (5.6448mhz) 001 = 12.288mhz (11.2896mhz) 010 = 24.576mhz (22.5792mhz) 011 = 49.152mhz (45.1584mhz) all other codes are reserved the frequencies in brackets apply for 44.1khz-related sample rates only (ie. sample_rate_n = 01xxx). 6 sysclk_ena 0 sysclk control 0 = disabled 1 = enabled sysclk should only be enabled after the applicable clock source has been configured and enabled. set this bit to 0 when reconfiguring the clock sources. 3:0 sysclk_src [3:0] 0100 sysclk source 0000 = mclk1 0001 = mclk2 0100 = fll1 0101 = fll2 1000 = aif1bclk 1001 = aif2bclk 1010 = aif3bclk all other codes are reserved
WM5102 production data w pd, may 2013, rev 4.0 216 register address bit label default description r258 (0102h) sample rate 1 4:0 sample_rate_ 1 [4:0] 10001 sample rate 1 select 00h = none 01h = 12khz 02h = 24khz 03h = 48khz 04h = 96khz 05h = 192khz 09h = 11.025khz 0ah = 22.05khz 0bh = 44.1khz 0ch = 88.2khz 0dh = 176.4khz 10h = 4khz 11h = 8khz 12h = 16khz 13h = 32khz all other codes are reserved r259 (0103h) sample rate 2 4:0 sample_rate_ 2 [4:0] 10001 sample rate 2 select register coding is same as sample_rate_1. r260 (0104h) sample rate 3 4:0 sample_rate_ 3 [4:0] 10001 sample rate 3 select register coding is same as sample_rate_1. r266 (010ah) sample rate 1 status 4:0 sample_rate_ 1_sts [4:0] 00000 sample rate 1 status (read only) register coding is same as sample_rate_1. r267 (010bh) sample rate 2 status 4:0 sample_rate_ 2_sts [4:0] 00000 sample rate 2 status (read only) register coding is same as sample_rate_1. r268 (010ch) sample rate 3 status 4:0 sample_rate_ 3_sts [4:0] 00000 sample rate 3 status (read only) register coding is same as sample_rate_1. r274 (0112h) async clock 1 10:8 async_clk_fr eq [2:0] 011 asyncclk frequency 000 = 6.144mhz (5.6448mhz) 001 = 12.288mhz (11.2896mhz) 010 = 24.576mhz (22.5792mhz) 011 = 49.152mhz (45.1584mhz) all other codes are reserved the frequencies in brackets apply for 44.1khz-related sample rates only (ie. asnyc_sample_rate_n = 01xxx). 6 async_clk_en a 0 asyncclk control 0 = disabled 1 = enabled asyncclk should only be enabled after the applicable clock source has been configured and enabled. set this bit to 0 when reconfiguring the clock sources.
production data WM5102 w pd, may 2013, rev 4.0 217 register address bit label default description 3:0 async_clk_sr c [3:0] 0101 asyncclk source 0000 = mclk1 0001 = mclk2 0100 = fll1 0101 = fll2 1000 = aif1bclk 1001 = aif2bclk 1010 = aif3bclk all other codes are reserved r275 (0113h) async sample rate 1 4:0 async_sample _rate_1 [4:0] 10001 async sample rate 1 select 00h = none 01h = 12khz 02h = 24khz 03h = 48khz 04h = 96khz 05h = 192khz 09h = 11.025khz 0ah = 22.05khz 0bh = 44.1khz 0ch = 88.2khz 0dh = 176.4khz 10h = 4khz 11h = 8khz 12h = 16khz 13h = 32khz all other codes are reserved r276 (0114h) async sample rate 2 4:0 async_sample _rate_2 [4:0] 10001 async sample rate 2 select register coding is same as async_sample_rate_1. r283 (011bh) async sample rate 1 status 4:0 async_sample _rate_1_sts [4:0] 00000 async sample rate 1 status (read only) register coding is same as async_sample_rate_1. r284 (011ch) async sample rate 2 status 4:0 async_sample _rate_2_sts [4:0] 00000 async sample rate 2 status (read only) register coding is same as async_sample_rate_1. r329 (0149h) output system clock 15 opclk_ena 0 opclk enable 0 = disabled 1 = enabled 7:3 opclk_div [4:0] 00h opclk divider 00h = divide by 1 01h = divide by 1 02h = divide by 2 03h = divide by 3 ? 1fh = divide by 31
WM5102 production data w pd, may 2013, rev 4.0 218 register address bit label default description 2:0 opclk_sel [2:0] 000 opclk source frequency 000 = 6.144mhz (5.6448mhz) 001 = 12.288mhz (11.2896mhz) 010 = 24.576mhz (22.5792mhz) 011 = 49.152mhz (45.1584mhz) all other codes are reserved the frequencies in brackets apply for 44.1khz-related sysclk rates only (ie. sample_rate_n = 01xxx). the opclk source frequency must be less than or equal to the sysclk frequency. r330 (014ah) output async clock 15 opclk_async_ ena 0 opclk_async enable 0 = disabled 1 = enabled 7:3 opclk_async_ div [4:0] 00h opclk_async divider 00h = divide by 1 01h = divide by 1 02h = divide by 2 03h = divide by 3 ? 1fh = divide by 31 2:0 opclk_async_ sel [2:0] 000 opclk_async source frequency 000 = 6.144mhz (5.6448mhz) 001 = 12.288mhz (11.2896mhz) 010 = 24.576mhz (22.5792mhz) 011 = 49.152mhz (45.1584mhz) all other codes are reserved the frequencies in brackets apply for 44.1khz-related asyncclk rates only (ie. async_sample_rate_n = 01xxx). the opclk_async source frequency must be less than or equal to the asyncclk frequency. r338 (0152h) rate estimator 1 4 trig_on_star tup 0 automatic sample rate detection start- up select 0 = do not trigger write sequence on initial detection 1 = always trigger the write sequencer on sample rate detection 3:1 lrclk_src [2:0] 000 automatic sample rate detection source 000 = aif1rxlrclk 001 = aif1txlrclk 010 = aif2rxlrclk 011 = aif2txlrclk 100 = aif3rxlrclk 101 = aif3txlrclk 110 = reserved 111 = reserved 0 rate_est_ena 0 automatic sample rate detection control 0 = disabled 1 = enabled
production data WM5102 w pd, may 2013, rev 4.0 219 register address bit label default description r339 (0153h) rate estimator 2 4:0 sample_rate_ detect_a [4:0] 00h automatic detection sample rate a (up to four different sample rates can be configured for automatic detection.) register coding is same as sample_rate_n. r340 (0154h) rate estimator 3 4:0 sample_rate_ detect_b [4:0] 00h automatic detection sample rate b (up to four different sample rates can be configured for automatic detection.) register coding is same as sample_rate_n. r341 (0155h) rate estimator 4 4:0 sample_rate_ detect_c [4:0] 00h automatic detection sample rate c (up to four different sample rates can be configured for automatic detection.) register coding is same as sample_rate_n. r342 (0156h) rate estimator 5 4:0 sample_rate_ detect_d [4:0] 00h automatic detection sample rate d (up to four different sample rates can be configured for automatic detection.) register coding is same as sample_rate_n. r3104 (0c20h) misc pad ctrl 1 13 mclk2_pd 0 mclk2 pull-down control 0 = disabled 1 = enabled r3105 (0c21h) misc pad ctrl 2 12 mclk1_pd 0 mclk1 pull-down control 0 = disabled 1 = enabled table 90 clocking control in aif slave modes, it is important to ensure the applicable clock domain (sysclk or asyncclk) is synchronised with the associated external lrclk. this can be achieved by selecting an mclk input that is derived from the same reference as the l rclk, or can be achieved by selecting the external bclk or lrclk signal as a reference input to one of the flls, as a source for sysclk or asyncclk. if the aif clock domain is not synchronised with the lrclk, then clicks arising from dropped or repeated audio samples will occur, due to the inherent tolerances of multiple, asynchronous, system clocks. see ?applications information? for fu rther details on valid clocking configurations.
WM5102 production data w pd, may 2013, rev 4.0 220 bclk and lrclk control the digital audio interfaces (aif1, aif2 and aif3 ) use bclk and lrclk signals for synchronisation. in master mode, these are output signals, generated by the WM5102. in slave mode, these are input signals to the WM5102. it is also possible to support mixed master/slave operation. the bclk and lrclk signals are controlled as illust rated in figure 65. see the ?digital audio interface control? section for further details of the relevant control registers. note that the bclk and lrclk signals are synchronised to sysclk or asynclk, depending upon the applicable clocking domain for the respective interface. see ?dig ital core? for further details. aif1_bclk_freq [4:0] f/n aif1bclk aif1lrclk aif1rx_bcpf [12:0] f/n gpio1 (aif1txlrclk) aif1tx_bcpf [12:0] sysclk master mode clock outputs f/n aif1_bclk_mstr aif1rx_lrclk_mstr aif1tx_lrclk_mstr aif2_bclk_freq [4:0] f/n aif2bclk aif2lrclk aif2rx_bcpf [12:0] f/n gpio2 (aif2txlrclk) aif2tx_bcpf [12:0] master mode clock outputs f/n aif2_bclk_mstr aif2rx_lrclk_mstr aif2tx_lrclk_mstr aif3_bclk_freq [4:0] f/n aif3bclk aif3lrclk aif3rx_bcpf [12:0] f/n gpio3 (aif3txlrclk) aif3tx_bcpf [12:0] master mode clock outputs f/n aif3_bclk_mstr aif3rx_lrclk_mstr aif3tx_lrclk_mstr asyncclk the clock reference for each aif is sysclk or asyncclk aifn is clocked from sysclk if aifn_rate < 1000 aifn is clocked from asyncclk if aifn_rate >= 1000 (see note below) (see note below) (see note below) figure 65 bclk and lrclk control control interface clocking register map access is possible with or without a system clock. clocking is provided from sysclk; the sysclk_src register selects the applicable sysclk source. see ?control interface? for further details of control register access. frequency locked loop (fll) two integrated flls are provided to support the clocking requirements of the WM5102. these can be enabled and configured independently according to the available reference clocks and the application requirements. the reference clock may be a hi gh frequency (eg. 12.288mhz) or low frequency (eg. 32.768khz). the fll is tolerant of jitter and may be used to gener ate a stable output clock from a less stable input reference. the fll characteristics are summarised in ?electrical characteristics?. note that the fll can be used to generate a free-running clock in the abs ence of an external reference source. this is described in the ?free-running fll mode? section below. configurable spr ead-spectrum modulation
production data WM5102 w pd, may 2013, rev 4.0 221 can be applied to the fll outputs, to control emi effects. each of the flls comprises two sub-systems - the ?main? loop and the ?synchr oniser? loop; these can be used together to maintain best frequency accuracy and noise (jitter) performance across multiple use-cases. the two-loop design enables the fll to sy nchronise effectively to an input clock that may be intermittent or noisy, whilst also achieving the performance benefits of a stable clock reference that may be asynchronous to the audio data. the main loop takes a constant and stable clock re ference as its input. for best performance, a high frequency (eg. 12.288mhz) reference is recommended. the synchroniser loop takes a separate clock refer ence as its input. the synchroniser input may be intermittent (eg. during voice calls only). the fll uses the synchroniser inpu t, when available, as the frequency reference. to achieve the designed performance advantage, the synchroniser input must be synchronous with the audio data. note that, if only a single clock input reference is used, this must be configured as the main fll input reference. the synchroniser c an be disabled in this case. the fll is enabled using the fll n _ena register bit (where n = 1 or 2 for the corresponding fll). the fll synchroniser is enabled using the fll n _sync_ena register bit. note that the other fll registers should be configured before enabling the fll; the fll n _ena and fll n _sync_ena register bits should be set as the final step of the fll n enable sequence. when changing fll settings, it is recommended that the digital circui t be disabled via fll n _ena and then re-enabled after the other register se ttings have been updated. w hen changing the input reference frequency f ref , it is recommended that the fll be reset by setting fll n _ena to 0. note that some of the fll configuration r egisters can be updated while the fll is enabled, as described below. as a general rule, however, it is recommended to configure the fll (and fll synchroniser, if applicable), before setting the corresponding _ena register bit(s). the fll configuration requirements are illustrated in figure 66. figure 66 fll configuration
WM5102 production data w pd, may 2013, rev 4.0 222 the procedure for configuring the f ll is described below. note that the configuration of the main fll path and the fll synchroniser path are very similar. one or both paths must be configured, depending on the application requirements: ? if a single clock input reference is used, then only the main fll path is required. ? if two clock input references are used, then t he constant or low-noise clock is configured on the main fll path, and the high-accuracy clo ck is configured on the fll synchroniser path. note that the synchroniser input must be synchronous with the audio data. the following description is applicable to fll1 and fll2. the associated register control fields are described in table 94 and table 95 respectively. the main input reference is selected using flln_r efclk_src. the synchroniser input reference is selected using flln_syncclk_src. the available opt ions in each case comprise mclk1, mclk2, slimclk, aifnbclk, aifnrxlrclk, or the output from another fll. the slimclk reference is controlled by an adaptiv e divider on the external slimclk input. the divider automatically adapts to the slimbus clock g ear, to provide a const ant reference frequency for the fll. see ?slimbus interface? for details. the fll n _refclk_div field controls a programmable divider on the main input reference. the fll n _syncclk_div field controls a programmable divi der on the synchroniser input reference. each input can be divided by 1, 2, 4 or 8. these regi sters should be set to bring each reference down to 13.5mhz or below. for best performance, it is recommended that the highest possible frequency - within the 13.5mhz limit - should be selected. the fll output frequency, relative to the main input reference f ref , is directly determined from fll n _fratio, fll n _outdiv and the real number represented by n.k. the integer value, n, is held in the fll n _n register field. the fracti onal portion, k, is determined by the ratio fll n _theta / fll n _lambda. the fll output frequency is generated according to the following equation: f out = (f vco / fll n _outdiv) the fll operating frequency, f vco is set according to the following equation: f vco = (f ref x n.k x fll n _fratio) f ref is the input frequency, as determined by fll n _refclk_div. f vco must be in the range 90mhz to 104mhz. fr equencies outside this range cannot be supported. note that the output frequencies that do not lie within the ranges quoted above cannot be guaranteed across the full range of dev ice operating conditions. in order to follow the above requirements for f vco , the value of fll n _outdiv should be selected according to the desired output f out . the divider, fll n _outdiv, must be set so that f vco is in the range 90mhz to 104mhz. supported settings of fll n _outdiv are noted in table 91. output frequency f out fll n _outdiv 22.5 mhz to 26 mhz 100 (divide by 4) 45 mhz to 50 mhz 010 (divide by 2) table 91 selection of fll n _outdiv
production data WM5102 w pd, may 2013, rev 4.0 223 the fll n _fratio field selects the frequency divi sion ratio of the fll input. the fll n _gain field is used to optimise the fll, according to the input frequency. these fields shoul d be set as described in table 92. reference frequency f ref fll n _fratio fll n _gain 1mhz - 13.5mhz 0h (divide by 1) 4h (16x gain) 256khz - 1mhz 1h (divide by 2) 2h (4x gain) 128khz - 256khz 2h (divide by 4) 0h (1x gain) 64khz - 128khz 3h (divide by 8) 0h (1x gain) less than 64khz 4h (divide by 16) 0h (1x gain) table 92 selection of fll n _fratio and fll n _gain in order to determine the remaining fll parameters, the fll operating frequency, f vco , must be calculated, as given by the following equation: f vco = (f out x fll n _outdiv) the value of n.k can then be determined as follows: n.k = f vco / (fll n _fratio x f ref ) note that, in the above equations: fll n _outdiv is the f out clock ratio. f ref is the input frequency, after division by fll n _refclk_div, where applicable. fll n _fratio is the f vco clock ratio (1, 2, 4, 8 or 16). the value of n is held in the fll n _n register field. the value of k is determined by the ratio fll n _theta / fll n _lambda. the fll n _n, fll n _theta and fll n _lambda fields are all coded as integers (lsb = 1). the flln_n and flln_theta values are applied to the fll when a ?1? is written to the flln_ctrl_upd bit. this makes it possible to updat e the two registers simultaneously, allowing the fll to be reconfigured without disabling the fll (p rovided that only these two registers require to be changed). the values of flln_theta and flln_lambda can be calculated as described later. a similar procedure applies for the deriviation of the fll synchroniser parameters - assuming that this function is used. the fll n _sync_fratio field selects the frequency divisi on ratio of the fll synchroniser input. the fll n _gain and fll n _sync_dfsat fields are used to optimis e the fll, according to the input frequency. these fields should be set as described in table 93. synchroniser frequency f sync fll n _sync_fratio flln_sync_gain flln_sync_dfsat 1mhz - 13.5mhz 0h (divide by 1) 4h (16x gain) 0 (wide bandwidth) 256khz - 1mhz 1h (divide by 2) 2h (4x gain) 0 (wide bandwidth) 128khz - 256khz 2h (divide by 4) 0h (1x gain) 0 (wide bandwidth) 64khz - 128khz 3h (divide by 8) 0h (1x gain) 1 (narrow bandwidth) less than 64khz 4h (divide by 16) 0h (1x gain) 1 (narrow bandwidth) table 93 selection of fll n _sync_fratio, fll n _sync_gain, fll n _sync_dfsat
WM5102 production data w pd, may 2013, rev 4.0 224 the fll operating frequency, f vco , is the same frequency calculated as described above. the value of n.k (sync) can then be determined as follows: n.k (sync) = f vco / (fll n _sync_fratio x f sync ) note that, in the above equations: f sync is the synchroniser input fr equency, after division by fll n _syncclk_div, where applicable. fll n _sync_fratio is the f vco clock ratio (1, 2, 4, 8 or 16). the value of n (sync) is held in the fll n _sync_n register field. the value of k (sync) is determined by the ratio fll n _sync_theta / fll n _sync_lambda. the fll n _sync_n, fll n _sync_theta and fll n _sync_lambda fields are all coded as integers (lsb = 1). in fractional mode (fll n _theta > 0), the register fields fll n _theta and fll n _lambda can be calculated as described below. note that an equivalent procedure is also used to derive the fll n _sync_theta and fll n _sync_lambda register values from the corresponding synchroniser parameters. calculate gcd(fll) using the ?gr eatest common denominator? function: gcd(fll) = gcd(fll n _fratio x f ref , f vco ) where gcd(x, y) is the greatest common denominator of x and y f ref is the input frequency, after division by fll n _refclk_div, where applicable. next, calculate fll n _theta and fll n _lambda using the following equations: fll n _theta = (f vco - (fll_n x fll n _fratio x f ref )) / gcd(fll) fll n _lambda = (fll n _fratio x f ref ) / gcd(fll) note that, in fractional mode, the values of fll n _theta and fll n _lambda must be co-prime (ie. not divisible by any common integer). the calculat ion above ensures that the values will be co-prime. the value of k must be a fraction less than 1 (ie. fll n _theta must be less than fll n _lambda). the fll control registers are de scribed in table 94 and table 95. ex ample settings for a variety of reference frequencies and output frequencies are shown in table 98. register address bit label default description r369 (0171h) fll1 control 1 0 fll1_ena 0 fll1 enable 0 = disabled 1 = enabled this should be set as the final step of the fll1 enable sequence, ie. after the other fll registers have been configured.
production data WM5102 w pd, may 2013, rev 4.0 225 register address bit label default description r370 (0172h) fll1 control 2 15 fll1_ctrl_up d 0 fll1 control update write ?1? to apply the fll1_n and fll1_theta register settings 9:0 fll1_n [9:0] 008h fll1 integer multiply for f ref (lsb = 1) note that fll1_n is only updated when a ?1? is written to fll1_ctrl_upd. r371 (0173h) fll1 control 3 15:0 fll1_theta [15:0] 0018h fll1 fractional multiply for f ref this field sets the numerator (multiply) part of the fll1_theta / fll1_lambda ratio. coded as lsb = 1. note that fll1_theta is only updated when a ?1? is written to fll1_ctrl_upd. r372 (0174h) fll1 control 4 15:0 fll1_lambda [15:0] 007dh fll1 fractional multiply for f ref this field sets the denominator (dividing) part of the fll1_theta / fll1_lambda ratio. coded as lsb = 1. r373 (0175h) fll1 control 5 10:8 fll1_fratio [2:0] 000 fll1 f vco clock divider 000 = 1 001 = 2 010 = 4 011 = 8 1xx = 16 3:1 fll1_outdiv [2:0] 010 fll1 f out clock divider 000 = reserved 001 = reserved 010 = divide by 2 011 = divide by 3 100 = divide by 4 101 = divide by 5 110 = divide by 6 111 = divide by 7 (f out = f vco / fll1_outdiv) r374 (0176h) fll1 control 6 7:6 fll1_refclk_d iv [1:0] 00 fll1 clock reference divider 00 = 1 01 = 2 10 = 4 11 = 8 mclk (or other input reference) must be divided down to <=13.5mhz. for lower power operation, the reference clock can be divided down further if desired.
WM5102 production data w pd, may 2013, rev 4.0 226 register address bit label default description 3:0 fll1_refclk_s rc 0000 fll1 clock source 0000 = mclk1 0001 = mclk2 0011 = slimclk 0100 = fll1 0101 = fll2 1000 = aif1bclk 1001 = aif2bclk 1010 = aif3bclk 1100 = aif1rxlrclk 1101 = aif2rxlrclk 1110 = aif3rxlrclk all other codes are reserved r377 (0179h) fll1 control 7 5:2 fll1_gain [3:0] 0000 fll1 gain 0000 = 1 0001 = 2 0010 = 4 0011 = 8 0100 = 16 0101 = 32 0110 = 64 0111 = 128 1000 to 1111 = 256 r385 (0181h) fll1 synchroni ser 1 0 fll1_sync_en a 0 fll1 synchroniser enable 0 = disabled 1 = enabled this should be set as the final step of the fll1 synchroniser enable sequence, ie. after the other synchroniser registers have been configured. r386 (0182h) fll1 synchroni ser 2 9:0 fll1_sync_n [9:0] 000h fll1 integer multiply for f sync (lsb = 1) r387 (0183h) fll1 synchroni ser 3 15:0 fll1_sync_th eta [15:0] 0000h fll1 fractional multiply for f sync this field sets the numerator (multiply) part of the fll1_sync_theta / fll1_sync_lambda ratio. coded as lsb = 1. r388 (0184h) fll1 synchroni ser 4 15:0 fll1_sync_la mbda [15:0] 0000h fll1 fractional multiply for f sync this field sets the denominator (dividing) part of the fll1_sync_theta / fll1_sync_lambda ratio. coded as lsb = 1. r389 (0185h) fll1 synchroni ser 5 10:8 fll1_sync_fr atio [2:0] 000 fll1 synchroniser f vco clock divider 000 = 1 001 = 2 010 = 4 011 = 8 1xx = 16
production data WM5102 w pd, may 2013, rev 4.0 227 register address bit label default description r390 (0186h) fll1 synchroni ser 6 7:6 fll1_syncclk _div [1:0] 00 fll1 synchroniser clock reference divider 00 = 1 01 = 2 10 = 4 11 = 8 mclk (or other input reference) must be divided down to <=13.5mhz. for lower power operation, the reference clock can be divided down further if desired. 3:0 fll1_syncclk _src 0000 fll1 synchroniser clock source 0000 = mclk1 0001 = mclk2 0011 = slimclk 0100 = fll1 0101 = fll2 1000 = aif1bclk 1001 = aif2bclk 1010 = aif3bclk 1100 = aif1rxlrclk 1101 = aif2rxlrclk 1110 = aif3rxlrclk all other codes are reserved r391 (0187h) fll1 synchroni ser 7 5:2 fll1_sync_gai n [3:0] 0000 fll1 synchroniser gain 0000 = 1 0001 = 2 0010 = 4 0011 = 8 0100 = 16 0101 = 32 0110 = 64 0111 = 128 1000 to 1111 = 256 0 fll1_sync_df sat 1 fll1 synchroniser bandwidth 0 = wide bandwidth 1 = narrow bandwidth table 94 fll1 register map register address bit label default description r401 (0191h) fll2 control 1 0 fll2_ena 0 fll2 enable 0 = disabled 1 = enabled this should be set as the final step of the fll2 enable sequence, ie. after the other fll registers have been configured. r402 (0192h) fll2 15 fll2_ctrl_up d 0 fll2 control update write ?1? to apply the fll2_n and fll2_theta register settings
WM5102 production data w pd, may 2013, rev 4.0 228 register address bit label default description control 2 9:0 fll2_n [9:0] 008h fll2 integer multiply for f ref (lsb = 1) note that fll2_n is only updated when a ?1? is written to fll2_ctrl_upd. r403 (0193h) fll2 control 3 15:0 fll2_theta [15:0] 0018h fll2 fractional multiply for f ref this field sets the numerator (multiply) part of the fll2_theta / fll2_lambda ratio. coded as lsb = 1. note that fll2_theta is only updated when a ?1? is written to fll2_ctrl_upd. r404 (0194h) fll2 control 4 15:0 fll2_lambda [15:0] 007dh fll2 fractional multiply for f ref this field sets the denominator (dividing) part of the fll2_theta / fll2_lambda ratio. coded as lsb = 1. r405 (0195h) fll2 control 5 10:8 fll2_fratio [2:0] 000 fll2 f vco clock divider 000 = 1 001 = 2 010 = 4 011 = 8 1xx = 16 3:1 fll2_outdiv [2:0] 010 fll2 f out clock divider 000 = reserved 001 = reserved 010 = divide by 2 011 = divide by 3 100 = divide by 4 101 = divide by 5 110 = divide by 6 111 = divide by 7 (f out = f vco / fll2_outdiv) r406 (0196h) fll2 control 6 7:6 fll2_refclk_d iv [1:0] 00 fll2 clock reference divider 00 = 1 01 = 2 10 = 4 11 = 8 mclk (or other input reference) must be divided down to <=13.5mhz. for lower power operation, the reference clock can be divided down further if desired.
production data WM5102 w pd, may 2013, rev 4.0 229 register address bit label default description 3:0 fll2_refclk_s rc 0000 fll2 clock source 0000 = mclk1 0001 = mclk2 0011 = slimclk 0100 = fll1 0101 = fll2 1000 = aif1bclk 1001 = aif2bclk 1010 = aif3bclk 1100 = aif1rxlrclk 1101 = aif2rxlrclk 1110 = aif3rxlrclk all other codes are reserved r409 (0199h) fll2 control 7 5:2 fll2_gain [3:0] 0000 fll2 gain 0000 = 1 0001 = 2 0010 = 4 0011 = 8 0100 = 16 0101 = 32 0110 = 64 0111 = 128 1000 to 1111 = 256 r417 (01a1h) fll2 synchroni ser 1 0 fll2_sync_en a 0 fll2 synchroniser enable 0 = disabled 1 = enabled this should be set as the final step of the fll2 synchroniser enable sequence, ie. after the other synchroniser registers have been configured. r418 (01a2h) fll2 synchroni ser 2 9:0 fll2_sync_n [9:0] 000h fll2 integer multiply for f sync (lsb = 1) r419 (01a3h) fll2 synchroni ser 3 15:0 fll2_sync_th eta [15:0] 0000h fll2 fractional multiply for f sync this field sets the numerator (multiply) part of the fll2_sync_theta / fll2_sync_lambda ratio. coded as lsb = 1. r420 (01a4h) fll2 synchroni ser 4 15:0 fll2_sync_la mbda [15:0] 0000h fll2 fractional multiply for f sync this field sets the denominator (dividing) part of the fll2_sync_theta / fll2_sync_lambda ratio. coded as lsb = 1. r421 (01a5h) fll2 synchroni ser 5 10:8 fll2_sync_fr atio [2:0] 000 fll2 synchroniser f vco clock divider 000 = 1 001 = 2 010 = 4 011 = 8 1xx = 16
WM5102 production data w pd, may 2013, rev 4.0 230 register address bit label default description r422 (01a6h) fll2 synchroni ser 6 7:6 fll2_syncclk _div [1:0] 00 fll2 synchroniser clock reference divider 00 = 1 01 = 2 10 = 4 11 = 8 mclk (or other input reference) must be divided down to <=13.5mhz. for lower power operation, the reference clock can be divided down further if desired. 3:0 fll2_syncclk _src 0000 fll2 synchroniser clock source 0000 = mclk1 0001 = mclk2 0011 = slimclk 0100 = fll1 0101 = fll2 1000 = aif1bclk 1001 = aif2bclk 1010 = aif3bclk 1100 = aif1rxlrclk 1101 = aif2rxlrclk 1110 = aif3rxlrclk all other codes are reserved r423 (01a7h) fll2 synchroni ser 7 5:2 fll2_sync_gai n [3:0] 0000 fll2 synchroniser gain 0000 = 1 0001 = 2 0010 = 4 0011 = 8 0100 = 16 0101 = 32 0110 = 64 0111 = 128 1000 to 1111 = 256 0 fll2_sync_df sat 1 fll2 synchroniser bandwidth 0 = wide bandwidth 1 = narrow bandwidth table 95 fll2 register map
production data WM5102 w pd, may 2013, rev 4.0 231 free-running fll mode the fll can generate a clock signal even when no exte rnal reference is available. this may be because the normal input reference has been interr upted, or may be during a standby or start-up period when no initial reference clock is available. free-running fll mode is enabled using the flln_fr eerun register. (note that flln_ena must also be enabled in free-running fll mode.) in free-running fll mode, the normal feedback mechanism of the fll is halted, and the fll oscillates independently of the external input reference(s). if the fll was previously operating normally, (wit h an input reference clock), then the fll output frequency will remain unchanged when free-running fll mode is enabled. if the fll was not previously configured, then t he fll output frequency will be as specified in the ?electrical characteristics? section. note that the fll integrator setting does not ensur e a specific output frequency for the fll across all devices and operating conditions ; a significant level of variation will apply, especially if the fll is operating independently of any input reference. note that the free-running fll clock may be sele cted as the sysclk source or asyncclk source as shown figure 64. the free-running fll mode is enabled using the register bits described in table 96. register address bit label default description r369 (0171h) fll1 control 1 1 fll1_freerun 1 fll1 free-running mode enable 0 = disabled 1 = enabled the fll feedback mechanism is halted in free-running mode, and the latest integrator setting is maintained r401 (0191h) fll2 control 1 1 fll2_freerun 0 fll2 free-running mode enable 0 = disabled 1 = enabled the fll feedback mechanism is halted in free-running mode, and the latest integrator setting is maintained table 96 free-running fll mode control
WM5102 production data w pd, may 2013, rev 4.0 232 spread spectrum fll control the WM5102 can apply modulation to the fll outputs, using spread spectrum techniques. this can be used to control the emi characteristics of the circuits that are clocked via the flls. each of the flls can be individually confi gured for triangle modulation, zero mean frequency modulation (zmfm) or dither. the amplitude and frequency parameters of the spread spectrum functions is also programmable, usi ng the registers described in table 97. register address bit label default description r393 (0189h) fll1 spread spectrum 5:4 fll1_ss_ampl [1:0] 00 fll1 spread spectrum amplitude controls the extent of the spread- spectrum modulation. 00 = 0.7% (triangle), 0.7% (zmfm, dither) 01 = 1.1% (triangle), 1.3% (zmfm, dither) 10 = 2.3% (triangle), 2.6% (zmfm, dither) 11 = 4.6% (triangle), 5.2% (zmfm, dither) 3:2 fll1_ss_freq [1:0] 00 fll1 spread spectrum frequency controls the spread spectrum modulation frequency in triangle mode. 00 = 439khz 01 = 878khz 10 = 1.17mhz 11 = 1.76mhz 1:0 fll1_ss_sel [1:0] 00 fll1 spread spectrum select 00 = disabled 01 = triangle 10 = zero mean frequency (zmfm) 11 = dither r425 (01a9h) fll2 spread spectrum 5:4 fll2_ss_ampl [1:0] 00 fll2 spread spectrum amplitude controls the extent of the spread- spectrum modulation. 00 = 0.7% (triangle), 0.7% (zmfm, dither) 01 = 1.1% (triangle), 1.3% (zmfm, dither) 10 = 2.3% (triangle), 2.6% (zmfm, dither) 11 = 4.6% (triangle), 5.2% (zmfm, dither) 3:2 fll2_ss_freq [1:0] 00 fll2 spread spectrum frequency controls the spread spectrum modulation frequency in triangle mode. 00 = 439khz 01 = 878khz 10 = 1.17mhz 11 = 1.76mhz 1:0 fll2_ss_sel [1:0] 00 fll2 spread spectrum select 00 = disabled 01 = triangle 10 = zero mean frequency (zmfm) 11 = dither table 97 fll spread spectrum control
production data WM5102 w pd, may 2013, rev 4.0 233 gpio outputs from fll for each fll, the WM5102 supports an ?fll clock ok? signal which, when asserted, indicates that the fll has started up and is providing an output clo ck. each fll also supports an ?fll lock? signal which indicates whether fll lock has been achieved. the fll clock ok status and fll lock status are inputs to the interrupt control circuit and can be used to trigger an interrupt event - see ?interrupts?. the fll clock ok and fll lock signals can be output directly on a gpio pin as an external indication of the fll status. see ?general purpose i nput / output? to configure a gpio pin for these functions. clock output signals derived from the fll can be output on a gpio pin. see ?general purpose input / output? to configure a gpio pin for this function. the fll clocking configuration is illustrated in figure 66. example fll calculation the following example illustrates how to derive the fll1 registers to generate 49.152 mhz output (f out ) from a 12.000 mhz reference clock (f ref ): ? set fll1_refclk_div in order to generate f ref <=13.5mhz: fll1_refclk_div = 00 (divide by 1) ? set fll1_outdiv for the required output frequency as shown in table 91:- f out = 49.152 mhz, therefore fll1_outdiv = 2h (divide by 2) ? set fll1_fratio for the given refer ence frequency as shown in table 92: f ref = 12mhz, therefore fll1_fratio = 0h (divide by 1) ? calculate f vco as given by f vco = f out x fll1_outdiv:- f vco = 49.152 x 2 = 98.304mhz ? calculate n.k as given by n.k = f vco / (fll1_fratio x f ref ): n.k = 98.304 / (1 x 12) = 8.192 ? determine fll1_n from the integer portion of n.k:- fll1_n = 8 (008h) ? determine gcd(fll), as given by gcd(fll) = gcd(fll1_fratio x f ref , f vco ): gcd(fll) = gcd(1 x 12000000, 98304000) = 96000 ? determine fll1_theta, as given by fll1_theta = (f vco - (fll1_n x fll1_fratio x f ref )) / gcd(fll): fll1_theta = (98304000 - (8 x 1 x 12000000)) / 96000 fll1_theta = 24 (0018h) ? determine fll_lambda, as given by fll1_lambda = (fll1_fratio x f ref ) / gcd(fll): fll1_lambda = (1 x 12000000) / 96000 fll1_lambda = 125 (007dh)
WM5102 production data w pd, may 2013, rev 4.0 234 example fll settings table 98 provides example fll settings for generating 49.152mhz or 24.576mhz sysclk from a variety of low and high frequency reference inputs. f source f out (mhz) f ref divider n.k fratio f vco (mhz) outdiv flln_n flln_ theta flln_ lambda 32.000 khz 49.152 1 192 16 98.304 2 0c0h 32.000 khz 24.576 1 192 16 98.304 4 0c0h 32.768 khz 49.152 1 187.5 16 98.304 2 0bbh 0001h 0002h 32.768 khz 24.576 1 187.5 16 98.304 4 0bbh 0001h 0002h 48 khz 49.152 1 128 16 98.304 2 080h 48 khz 24.576 1 128 16 98.304 4 080h 128 khz 49.152 1 96 8 98.304 2 060h 128 khz 24.576 1 96 8 98.304 4 060h 512 khz 49.152 1 96 2 98.304 2 060h 512 khz 24.576 1 96 2 98.304 4 060h 1.536 mhz 49.152 1 64 1 98.304 2 040h 1.536 mhz 24.576 1 64 1 98.304 4 040h 3.072 mhz 49.152 1 32 1 98.304 2 020h 3.072 mhz 24.576 1 32 1 98.304 4 020h 11.2896 49.152 1 8.7075 1 98.304 2 008h 0068h 0093h 11.2896 24.576 1 8.7075 1 98.304 4 008h 0068h 0093h 12.000 mhz 49.152 1 8.192 1 98.304 2 008h 0018h 007dh 12.000 mhz 24.576 1 8.192 1 98.304 4 008h 0018h 007dh 12.288 mhz 49.152 1 8 1 98.304 2 008h 12.288 mhz 24.576 1 8 1 98.304 4 008h 13.000 mhz 49.152 1 7.5618 1 98.304 2 007h 0391h 0659h 13.000 mhz 24.576 1 7.5618 1 98.304 4 007h 0391h 0659h 19.200 mhz 49.152 2 10.24 1 98.304 2 00ah 0006h 0019h 19.200 mhz 24.576 2 10.24 1 98.304 4 00ah 0006h 0019h 24 mhz 49.152 2 8.192 1 98.304 2 008h 0018h 007dh 24 mhz 24.576 2 8.192 1 98.304 4 008h 0018h 007dh 26 mhz 49.152 2 7.5618 1 98.304 2 007h 0391h 0659h 26 mhz 24.576 2 7.5618 1 98.304 4 007h 0391h 0659h 27 mhz 49.152 2 7.2818 1 98.304 2 007h 013dh 0465h 27 mhz 24.576 2 7.2818 1 98.304 4 007h 013dh 0465h f out = (f source / f ref divider) * n.k * fratio / outdiv the values of n and k are contained in the flln_n, flln_theta and flln_lambda r egisters as shown above. see table 94 and table 95 for the coding of the flln_r efclk_div, flln_fratio and flln_outdiv registers. table 98 example fll settings
production data WM5102 w pd, may 2013, rev 4.0 235 control interface the WM5102 is controlled by writing to its control r egisters. readback is available for all registers. two independent control interfaces are provided, gi ving flexible capability as described below. note that the slimbus interface also supports read/wr ite access to the WM5102 control registers - see ?slimbus interface?. note that the control interface function can be s upported with or without system clocking. where applicable, the register map access is synchronis ed with sysclk in order to ensure predictable operation of cross-domain functions. see ?clocking and sample rates? for further details of control interface clocking. when sysclk is present and enabled, register access is possible on all of the control interfaces (including slimbus) simultaneously. when sysclk is disabled, then register access will only be supported on whichever interface (i2c, spi, or slimbus) is the first to attempt any regi ster access after sysclk has stopped. full access via all interfaces will be restored when sysclk is enabled. the WM5102 executes a boot sequence following power-on reset (por), hardware reset, software reset or wake-up (from sleep mode). note that control register writes should not be attempted until the boot sequence has completed. see ?power-on reset (por)? for further details. the WM5102 performs automatic checks to confirm that the control interface does not attempt a read or write operation to an invalid r egister address. the control interf ace address error condition can be monitored using the gpio and/or interrupt func tions. see ?general purpose input / output? and ?interrupts? for further details. control interface 1 (cif1) is a 2-wire (i 2c) interface, comprising the following pins: ? cif1sda - serial interface data input/output ? cif1sclk - serial interface clock input ? cif1addr - logic level controlling the i2c device id control interface 2 (cif2) is a 4-wire ( spi) interface, comprising the following pins: ? cif2mosi - spi data input ? cif2miso - spi data output ? cif2sclk - spi clock input ? cif1ss - spi slave select input (active low) a detailed description of the 2-wire (i2c) interfac e and 4-wire (spi) interfaces is provided in the following sections. the control interface confi guration registers are described in table 99. register address bit label default description r8 (08h) ctrl if spi cfg 1 4 spi_cfg 1 cif2miso pin configuration (applies to spi mode only) 0 = cmos 1 = wired ?or?. 1:0 spi_auto_inc [1:0] 01 cif2 spi address auto-increment select 00 = disabled 01 = increment by 1 on each access 10 = increment by 2 on each access 11 = increment by 3 on each access
WM5102 production data w pd, may 2013, rev 4.0 236 register address bit label default description r9 (09h) ctrl if i2c1 cfg 1 1:0 i2c1_auto_in c [1:0] 01 cif1 i2c address auto-increment select 00 = disabled 01 = increment by 1 on each access 10 = increment by 2 on each access 11 = increment by 3 on each access r3105 (0c21h) misc pad ctrl 2 0 addr_pd 1 cif1addr pull-down enable 0 = disabled 1 = enabled table 99 control interface configuration 2-wire (i2c) control mode the 2-wire (i2c) control interface mode is supported on cif1 only, and uses the corresponding sclk, sda pins. the addr pin is also used to select the i2c device id. in 2-wire (i2c) mode, the WM5102 is a slave device on the control interface; sclk is a clock input, while sda is a bi-directional data pin. to allow arbitr ation of multiple slaves (and/or multiple masters) on the same interface, the WM5102 transmits logic 1 by tri-stating the sda pin, rather than pulling it high. an external pull-up resistor is required to pull the sda line high so that the logic 1 can be recognised by the master. in order to allow many devices to share a singl e 2-wire control bus, ever y device on the bus has a unique 8-bit device id (this is not the same as the address of each register in the WM5102). the cif1 device id is selectable using the cif1a ddr pin, as described in table 100. the lsb of the device id is the read/write bit; this bit is se t to logic 1 for ?read? and logic 0 for ?write?. the cif1addr logic level is referenced to the dbv dd1 power domain. an internal pull-down resistor is enabled by default on the cif1addr pin; this c an be configured using the addr_pd register bit described in table 99. cif1addr device id (cif1) logic 0 0011 010x = 34h (write) / 35h (read) logic 1 0011 011x = 36h (write) / 37h (read) table 100 control interface device id selection the WM5102 operates as a slave device only. the controller indicates the start of data transfer with a high to low transition on sda while sclk remains hi gh. this indicates that a device id, register address and data will follow. the WM5102 responds to t he start condition and shifts in the next eight bits on sda (8-bit device id, including read/write bit, msb first). if the dev ice id received matches the device id of the WM5102, then the WM5102 responds by pulling sda low on the next clock pulse (ack). if the device id is not re cognised or the r/w bit is set incorrectly, the WM5102 returns to the idle condition and waits for a new start condition and valid address. if the device id matches the device id of the WM5102, the data transfer continues as described below. the controller indicates the end of data trans fer with a low to high transition on sda while sclk remains high. after receiving a complete address and data sequence the WM5102 returns to the idle state and waits for another start condition. if a start or stop condition is detected out of sequence at any point during data transfer (i.e. sda changes while sclk is high), the device returns to the idle condition.
production data WM5102 w pd, may 2013, rev 4.0 237 the WM5102 supports the following read and write operations: ? single write ? single read ? multiple write using auto-increment ? multiple read using auto-increment the sequence of signals associated with a single regi ster write operation is illustrated in figure 67. figure 67 control interface 2-wire (i2c) register write the sequence of signals associated with a single regi ster read operation is illustrated in figure 68. figure 68 control interface 2-wire (i2c) register read the control interface also supports other register operations, as listed above. the interface protocol for these operations is summarised below. the terminology used in the following figures is detailed in table 101. note that, for multiple write and multiple read operations, the auto-increment option must be enabled. this feature is enabled by default, as noted in table 99.
WM5102 production data w pd, may 2013, rev 4.0 238 terminology description s start condition sr repeated start a acknowledge (sda low) a not acknowledge (sda high) p stop condition r/w readnotwrite 0 = write 1 = read [white field] data flow from bus master to WM5102 [grey field] data flow from WM5102 to bus master table 101 control interface (i2c) terminology figure 69 single register write to specified address figure 70 single register read from specified address figure 71 multiple register write to specified address using auto-increment
production data WM5102 w pd, may 2013, rev 4.0 239 figure 72 multiple register read from specified address using auto-increment figure 73 multiple register read from last address using auto-increment continuous read and write modes enable multiple regi ster operations to be scheduled faster than is possible with single register operations. the aut o-increment function supports selectable address increments for each successive regist er access. this function is c ontrolled using the i2c1_auto_inc register. auto-increment (by 1) is enabl ed by default, as described in table 99.
WM5102 production data w pd, may 2013, rev 4.0 240 4-wire (spi) control mode the 4-wire (spi) control interface mode is s upported on cif2 only, and uses the corresponding ss , sclk, mosi and miso pins. the miso output pin can be configured as cmos or ?wired or?, as described in table 99. in cmos mode, miso is driven low when not outputting regi ster data bits. in ?wired or? mode, miso is undriven (high impedance) when not outputting register data bits. in write operations (r/w=0), all mosi bi ts are driven by the controlling device. in read operations (r/w=1), the mosi pin is ignor ed following receipt of the valid register address. miso is driven by the WM5102. continuous read and write modes enable multiple regi ster operations to be scheduled faster than is possible with single register operations. the aut o-increment function supports selectable address increments for each successive register access. th is function is controll ed using the spi_auto_inc register. auto-increment (by 1) is enabl ed by default, as described in table 99. when auto-increment is enabled, the WM5102 will incr ement the register address at the end of the sequences illustrated below, and every 16 clock cycles thereafter, for as long as ss is held low and sclk is toggled. successive data words c an be input/output every 16 clock cycles. the 4-wire (spi) protocol is illustrated in figure 74 and figure 75. figure 74 control interface 4-wire (spi) register write figure 75 control interface 4-wire (spi) register read
production data WM5102 w pd, may 2013, rev 4.0 241 control write sequencer the control write sequencer is a programmable unit that forms part of the WM5102 control interface logic. it provides the ability to perform a sequence of register write operations with the minimum of demands on the host processor - the sequence may be in itiated by a single operation from the host processor and then left to execute independently. default sequences for pop-suppressed start- up and shut-down of each headphone/earpiece output driver are provided (these are scheduled automatically when the re spective output paths are enabled or disabled). other control s equences can be programmed, and may be associated with jack detect, wake-up or sample rate detection functions - these sequences are automatically scheduled whenever a corresponding event is detected. when a sequence is initiated, the sequencer performs a series of pre-defined register writes. the ?start index? of a control sequence within the s equencer?s memory may be commanded directly by the host processor. in the case of a headphone or earpiece enable/disable event, or sequences associated with jack detect, wake-up or sample rate detection, the applicable ?start index? is held in a user-programmed control register for each sequence. the control write sequencer may be triggered in a number of ways, as described above. multiple sequences will be queued if necessary, and each is scheduled in turn. when all of the queued sequences have completed, the sequencer stops, and an interrupt status flag is asserted. a valid clock (sysclk) must be enabled whenever a control write sequence is scheduled. see ?clocking and sample rates? for further details. initiating a sequence the register fields associated with running the control write sequencer are described in table 102. the write sequencer is enabled using the wseq_ena bit. the index location of the first command in the selected sequence is held in the wseq_start_index register. writing a ?1? to the wseq_start bit commands the sequencer to execute a control sequence, starting at the given index. note that, if the sequencer is already runni ng, then the wseq_start command will be queued, and will be executed later when the sequencer becomes available. the write sequencer can be interrupted by writing a ?1? to the wseq_abort bit. note that this command will only abort a sequence that is current ly running; if other sequence commands are pending and not yet started, these sequences will not be aborted by writing to the wseq_abort bit. the write sequencer stores up to 256 register write commands. these are defined in registers r12288 (3000h) to r12799 (31ffh). each of the 256 possible commands is defined in 2 control registers - see table 108 for a description of these registers. register address bit label default description r22 (0016h) write sequencer ctrl 0 11 wseq_abort 0 writing a 1 to this bit aborts the current sequence. 10 wseq_start 0 writing a 1 to this bit starts the write sequencer at the index location selected by wseq_start_index. at the end of the sequence, this bit will be reset by the write sequencer. 9 wseq_ena 0 write sequencer enable 0 = disabled 1 = enabled only applies to sequences triggered using the wseq_start bit.
WM5102 production data w pd, may 2013, rev 4.0 242 register address bit label default description 8:0 wseq_start_i ndex [8:0] 000h sequence start index this field contains the index location in the sequencer memory of the first command in the selected sequence. only applies to sequences triggered using the wseq_start bit. valid from 0 to 255 (0ffh). table 102 write sequencer control - initiating a sequence automatic sample rate detection sequences the WM5102 supports automatic sample rate detection on the digital audio interfaces (aif1, aif2 and aif3), when operating in aif slave mode. automa tic sample rate detection is enabled using the rate_est_ena register bit (see table 90). up to four audio sample rates can be configured for automatic detection; these sample rates are selected using the sample_rate_detect_n register s. if one of the selected audio sample rates is detected, then the control write sequencer will be tr iggered. the applicable start index location within the sequencer memory is separately conf igurable for each detected sample rate. the wseq_sample_rate_detect_a_index regi ster defines the sequencer start index corresponding to the sample_rate_detect_a sample rate. equivalent start index values are defined for the other sample rates, as described in table 103. note that a sequencer start index of 1ffh w ill cause the respective sequence to be aborted. the automatic sample rate detection contro l sequences are undefined following power-on reset (por), but can be user-programmed after power-up. note that all control sequences are maintained in the sequencer memory through hardware reset, software reset and in sleep mode. see ?clocking and sample rates? for further details of the automatic sample rate detection function. register address bit label default description r97 (0061h) sample rate sequence select 1 8:0 wseq_sample _rate_detect _a_index [8:0] 1ffh sample rate a write sequence start index this field contains the index location in the sequencer memory of the first command in the sequence associated with sample rate a detection. valid from 0 to 255 (0ffh). r98 (0062h) sample rate sequence select 2 8:0 wseq_sample _rate_detect _b_index [8:0] 1ffh sample rate b write sequence start index this field contains the index location in the sequencer memory of the first command in the sequence associated with sample rate b detection. valid from 0 to 255 (0ffh). r99 (0063h) sample rate sequence select 3 8:0 wseq_sample _rate_detect _c_index [8:0] 1ffh sample rate c write sequence start index this field contains the index location in the sequencer memory of the first command in the sequence associated with sample rate c detection. valid from 0 to 255 (0ffh).
production data WM5102 w pd, may 2013, rev 4.0 243 register address bit label default description r100 (0064h) sample rate sequence select 4 8:0 wseq_sample _rate_detect _d_index [8:0] 1ffh sample rate d write sequence start index this field contains the index location in the sequencer memory of the first command in the sequence associated with sample rate d detection. valid from 0 to 255 (0ffh). table 103 write sequencer control - automatic sample rate detection jack detect, gpio, micdet clamp, and wake-up sequences the WM5102 supports external accessory detection and gpio functions. the jd1 signal (associated with external accessory detection) and the gp5 signal (associated with the gpio5 pin) can be used to trigger the control write sequencer. the jd1 signal is configured using the register bits described in t able 67. the gp5 signal is derived from the gpio5 pin, which is configured usi ng the register bits described in table 76. the micdet clamp is controlled by the jd1 and/or gp5 signals, as described in table 68. the micdet clamp status can also be used to trigger the control write sequencer. a control write sequence can be associated with a rising edge and/or a falling edge of the jd1, gp5 or micdet clamp. this is c onfigured using the register bits described in table 75. if one of the selected logic conditions is detected, then the control write sequencer will be triggered. the applicable start index location within the sequenc er memory is separatel y configurable for each logic condition. the wseq_gp5_rise_index regist er defines the sequencer star t index corresponding to a gp5 rising edge event. equivalent start index values are defined for the other logic conditions, as described in table 104. note that a sequencer start index of 1ffh w ill cause the respective sequence to be aborted. the jd1, gp5 and micdet clamp control s equences are undefined following power-on reset (por), but can be user-programmed after power-up. note that all control sequences are maintained in the sequencer memory through hardware reset, software reset and in sleep mode. see ?low power sleep configuration? for further details of the jd1, gp5 and micdet clamp status signals. see also ?general purpose input / output? for details of the gpio5 pin. register address bit label default description r102 (0066h) always on triggers sequence select 1 8:0 wseq_micd_cl amp_rise_inde x [8:0] 1ffh micdet clamp (rising) write sequence start index this field contains the index location in the sequencer memory of the first command in the sequence associated with micdet clamp (rising) detection. valid from 0 to 255 (0ffh). r103 (0067h) always on triggers sequence select 2 8:0 wseq_micd_cl amp_fall_inde x [8:0] 1ffh micdet clamp (falling) write sequence start index this field contains the index location in the sequencer memory of the first command in the sequence associated with micdet clamp (falling) detection. valid from 0 to 255 (0ffh). r104 (0068h) always on triggers sequence select 3 8:0 wseq_gp5_ris e_index [8:0] 1ffh gp5 (rising) write sequence start index this field contains the index location in the sequencer memory of the first command in the sequence associated with gp5 (rising) detection. valid from 0 to 255 (0ffh).
WM5102 production data w pd, may 2013, rev 4.0 244 register address bit label default description r105 (0069h) always on triggers sequence select 4 8:0 wseq_gp5_fal l_index [8:0] 1ffh gp5 (falling) write sequence start index this field contains the index location in the sequencer memory of the first command in the sequence associated with gp5 (falling) detection. valid from 0 to 255 (0ffh). r106 (006ah) always on triggers sequence select 5 8:0 wseq_jd1_ris e_index [8:0] 1ffh jd1 (rising) write sequence start index this field contains the index location in the sequencer memory of the first command in the sequence associated with jd1 (rising) detection. valid from 0 to 255 (0ffh). r107 (006bh) always on triggers sequence select 6 8:0 wseq_jd1_fal l_index [8:0] 1ffh jd1 (falling) write sequence start index this field contains the index location in the sequencer memory of the first command in the sequence associated with jd1 (falling) detection. valid from 0 to 255 (0ffh). table 104 write sequencer control - jd1, gp5 and micdet clamp a valid clock (sysclk) must be enabled whenever a control write sequence is scheduled. if the jd1, gp5 or micdet clamp trigger status bi ts are associated with the control write sequencer (using the register bits in table 75) and also confi gured as wake-up events (using the register bits in table 74), then the boot sequence must be progra mmed to configure and enable sysclk. (note that the default sysclk frequency must be used in this case.) the boot sequence (see below) is scheduled as part of the wake-up transition, and provides the capability to configure sysclk (and other register settings) prior to the control write sequencer being triggered. note that, if the control write sequencer is triggered during normal operation, then sysclk will typically be already available, and no additional requirements will apply. drc signal detect sequences the dynamic range control (drc) function within the WM5102 digital core pr ovides a configurable signal detect function. this allows the signal le vel at the drc input to be monitored and used to trigger other events. the drc signal detect function is enabled and configured using the regist er fields described in table 14. a control write sequence can be associated with a rising edge and/or a falling edge of the drc signal detect output. this is enabled using the drc1_wseq_sig_det_ena register bit. when the drc signal detect sequence is enabled, the control write sequencer will be triggered whenever the signal detect output transitions (high or low). the applicable start index location within the sequencer memory is separately c onfigurable for each logic condition. the wseq_sig_det_rise_seq_ind ex register defines the sequenc er start index corresponding to a drc signal detect rising edge ev ent, as described in table 105. the wseq_sig_det_fall_seq_index r egister defines the sequencer start index corresponding to a drc signal detect falling edge event. note that a sequencer start index of 1ffh w ill cause the respective sequence to be aborted. the drc signal detect sequences cannot be independently enabled for rising and falling edges. instead, a start index of 1ffh can be used to di sable the sequence for either edge, if required.
production data WM5102 w pd, may 2013, rev 4.0 245 the drc signal detect control sequences are undef ined following power-on reset (por), but can be user-programmed after power-up. note that a ll control sequences are maintained in the sequencer memory through hardware reset, software reset and in sleep mode. see ?digital core? for further details of the dynamic range control (drc) function. register address bit label default description r110 (006eh) trigger sequence select 32 8:0 wseq_drc1_si g_det_rise_in dex [8:0] 1ffh drc1 signal detect (rising) write sequence start index this field contains the index location in the sequencer memory of the first command in the sequence associated with drc1 signal detect (rising) detection. valid from 0 to 255 (0ffh). r111 (006fh) trigger sequence select 33 8:0 wseq_drc1_si g_det_fall_in dex [8:0] 1ffh drc1 signal detect (falling) write sequence start index this field contains the index location in the sequencer memory of the first command in the sequence associated with drc1 signal detect (falling) detection. valid from 0 to 255 (0ffh). table 105 write sequencer control - drc signal detect boot sequence the WM5102 executes a boot sequence following power-on reset (por), hardware reset, software reset or wake-up (from sleep mode). see ?power-on reset (por)? and ?hardware reset, software reset, wake-up, and device id? for further details. the boot sequence is undefined following power-on re set (por), but can be user-programmed after power-up. note that all control sequences are ma intained in the sequencer memory through hardware reset, software reset and in sleep mode. if the boot sequence is programmed to enable sy sclk, note that the default sysclk frequency must be used. if a different sysclk frequency is r equired, this must be configured after the boot sequence has completed. the start index location of the the boot sequence is 192 (0c0h). the boot sequence can be commanded at any time by writing ?1? to the wseq_boot_start bit. register address bit label default description r24 (0018h) write sequencer ctrl 2 1 wseq_boot_s tart 0 writing a 1 to this bit starts the write sequencer at the index location configured for the boot sequence. the boot sequence start index is 192 (0c0h). table 106 write sequencer control - boot sequence
WM5102 production data w pd, may 2013, rev 4.0 246 sequencer outputs and readback the status of the write sequencer can be read using the wseq_busy and wseq_current_index registers, as described in table 107. when the wseq_busy bit is asserted, this i ndicates that the write sequencer is busy. the index address of the most recent wr ite sequencer command can be read from the wseq_current_index field. this can be used to provide a precise indication of the write sequencer progress. register address bit label default description r23 (0017h) write sequencer ctrl 1 9 wseq_busy (read only) 0 sequencer busy flag (read only). 0 = sequencer idle 1 = sequencer busy 8:0 wseq_curren t_index [8:0] (read only) 000h sequence current index. this indicates the memory location of the most recently accessed command in the write sequencer memory. coding is the same as wseq_start_index. table 107 write sequencer control - status readback the write sequencer status is an input to the inte rrupt control circuit and can be used to trigger an interrupt event - see ?interrupts?. the write sequencer status can be output directly on a gpio pin as an external indication of the write sequencer. see ?general purpose input / output ? to configure a gpio pin for this function. programming a sequence a control write sequence comprises a series of write operations to data bits (o r groups of bits) within the control register map. each write operation is def ined by a block of 2 registers, each containing 5 fields, as described below. the block of 2 registers is replicated 256 times, defining each of the s equencer?s 256 possible index addresses. many sequences can be stored in the s equencer memory at the same time, with each assigned a unique range of index addresses. the wseq_delayn register is used to identify t he ?end of sequence? positi on, as described below. note that, in the following descriptions, the term ? n ? denotes the sequencer index address (valid from 0 to 255). wseq_data_width n is a 3-bit field which identifies the width of the data block to be written. note that the maximum value of this field selects a width of 8-bits; writing to regi ster fields greater than 8 bits wide must be performed using two s eparate operations of the write sequencer. wseq_addr n is a 13-bit field containing the register address in which the data should be written. wseq_delay n is a 4-bit field which controls the wait ing time between the current step and the next step in the sequence (ie. the delay occurs after the wr ite in which it was called). the total delay time per step (including execution) is defined below, giving a useful range of execution/delay times from 3.3 ? s up to 1s per step. setting this field to 0xf identifies the step as the last in the sequence. if wseq_delayn = 0h or fh, the step execution time is 3.3s for all other values, the step ex ecution time is 61.44s x ((2 wseq_delay ) - 1) wseq_data_start n is a 4-bit field which identifies the lsb position within the selected control register to which the data should be writt en. for example, setting wseq_data_start n = 0100 will
production data WM5102 w pd, may 2013, rev 4.0 247 select bit 4 as the lsb position of the data to be written. wseq_data n is an 8-bit field which contai ns the data to be written to the selected control register. the wseq_data_width n field determines how many of thes e bits are written to the selected control register; the most significant bits (above the number indicated by wseq_data_width n ) are ignored. the register definitions for step 0 are described in table 108. the equivalent definitions also apply to step 1 through to step 255, in the subsequent register address locations. register address bit label default description r12288 (3000h) wseq sequence 1 15:13 wseq_data_ width0 [2:0] 000 width of the data block written in this sequence step. 000 = 1 bit 001 = 2 bits 010 = 3 bits 011 = 4 bits 100 = 5 bits 101 = 6 bits 110 = 7 bits 111 = 8 bits 12:0 wseq_addr0 [12:0] 0000h control register address to be written to in this sequence step. r12289 (3001h) wseq sequence 2 15:12 wseq_delay0 [3:0] 0000 time delay after executing this step. 00h = 3.3us 01h to 0eh = 61.44us x ((2^wseq_delay)-1) 0fh = end of sequence marker 11:8 wseq_data_s tart0 [3:0] 0000 bit position of the lsb of the data block written in this sequence step. 0000 = bit 0 ? 1111 = bit 15 7:0 wseq_data0 [7:0] 00h data to be written in this sequence step. when the data width is less than 8 bits, then one or more of the msbs of wseq_data n are ignored. it is recommended that unused bits be set to 0. table 108 write sequencer control - programming a sequence sequencer memory definition the write sequencer memory defines up to 256 write operations; these are indexed as 0 to 255 in the sequencer memory map. following power-on reset (por), the sequence memory will contain only the headphone/earpiece enable and headphone/earpiece disable sequence def initions. the remainder of the sequence memory will be undefined on power-up. user-defined sequences can be progr ammed after power-up. note that all control sequences are maintained in the sequencer memory through hardware reset, software reset and in sleep mode. the default control sequences can be ov erwritten in the sequencer memory, if required. note that the headphone and earpiece output path enable registers (hpn x_ena, epn_ena) will always trigger the write sequencer (at the pre-det ermined start index addresses). writing ?1? to the wseq_load_mem bit will clear the sequencer memory to the por state.
WM5102 production data w pd, may 2013, rev 4.0 248 register address bit label default description r24 (0018h) write sequencer ctrl 2 0 wseq_load_ mem 0 writing a 1 to this bit resets the sequencer memory to the por state. table 109 write sequencer control - load memory control user-defined sequences must be a ssigned space within the write sequencer memory. the start index for the user-defined sequences is configured using the register s described in table 103 and table 104. the boot sequence has a fixed start address, as referenced in table 106. the sequencer memory is illustrated in figure 76. the pre-programmed sequencer index locations are highlighted. user-defined sequences should be programmed in other areas of the sequencer memory. figure 76 write sequencer memory further details of the pre-programmed sequencer index locations are provided in table 110. sequence name start index default sequence index ranges hpout1l enable 0 (000h) 0 to 11 hpout1l disable 24 (018h) 24 to 27 hpout1r enable 32 (020h) 32 to 43 hpout1r disable 56 (038h) 56 to 59 hpout2l enable 64 (040h) 64 to 74 hpout2l disable 88 (058h) 88 to 91 hpout2r enable 96 (060h) 96 to 107 hpout2r disable 120 (078h) 120 to 123 epout enable 128 (080h) 128 to 137 epout disable 144 (090h) 144 to 147 boot sequence 192 (0c0h) table 110 default sequencer memory allocation
production data WM5102 w pd, may 2013, rev 4.0 249 charge pumps, regulators and voltage reference the WM5102 incorporates two charge pump circui ts and two ldo regulator circuits to generate supply rails for internal functi ons and to support external micr ophone requirements. the WM5102 also provides three micbias generators which provide lo w noise reference voltages suitable for biasing electret condenser (ecm) type micr ophones or powering digital microphones. refer to the ?applications information? section for recommended external components. charge pumps and ldo2 regulator charge pump 1 (cp1) is used to generate the positive and negative supply rails for the analogue output drivers. cp1 is enabled automatically by the WM5102 when required by the output drivers. charge pump 2 (cp2) powers ldo2, which provides the supply rail for analogue input circuits and for the micbias generators. cp2 and ldo2 are enabled using the cp2_ena register bit. the 32khz clock must be configured and enabled when using cp2. see ?clocking and sample rates? for details of the system clocks. when cp2 and ldo2 are enabled, the micvdd voltage can be selected using the ldo2_vsel control field. note that, when one or more of the micbias generators is operating in normal (regulator) mode, then the micvdd voltage must be at least 200mv greater than the highest selected micbiasn output voltage(s). when cp2 and ldo2 are enabled, an internal bypa ss path may be selected, connecting the micvdd pin directly to the cpvdd supply. this path is controlled using the cp2_bypass register. note that the bypass path is only supported when cp2 is enabled. when cp2 is disabled, the cp2v out pin can be configured to be floating or to be actively discharged. this is selected us ing the cp2_disch register bit. when ldo2 is disabled, the mi cvdd pin can be configured to be floating or to be actively discharged. this is selected usi ng the ldo2_disch register bit. the micvdd pin is connected to the output of ldo2 . note that the micvdd does not support direct connection to an external suppl y; micvdd is always powered internally to the WM5102. the charge pumps and ldo2 regulator circuits are illustrated in figure 77. the associated register control bits are described in table 111. note that decoupling capacitors and flyback capacitor s are required for these circuits. refer to the ?applications information? secti on for recommended external components. micbias bias (micbias) control there are three micbias generators which provide low noise referenc e voltages suitable for biasing electret condenser (ecm) ty pe microphones or powering digi tal microphones. refer to the ?applications information? secti on for recommended external components. the micbias generators are powered from micvdd, which is generated by an internal charge pump and ldo, as illustrated in figure 77. the micbias outputs can be independently enabled using the micb n _ena register bits (where n = 1, 2 or 3 for micbias1, 2 or 3 respectively). when a micbias output is disabled, the output pin c an be configured to be floating or to be actively discharged. this is selected using the micb n _disch register bits. the micbias generators can each operate as a voltage regulator or in bypass mode. the applicable mode is selected using the micb n _bypass registers. in regulator mode, the output voltage is selected using the micb n _lvl register bits. in this mode, micvdd must be at least 200mv greater than the required micbias output voltages. the micbias
WM5102 production data w pd, may 2013, rev 4.0 250 outputs are powered from the micvdd pin, and use the internal bandgap circuit as a reference. in regulator mode, the micbias regulators ar e designed to operate without external decoupling capacitors. the regulators can be configured to support a capacitive load if required, using the micbn_ext_cap register bits. (this may be appr opriate for a digital microphone supply.) it is important that the external capacitance is com patible with the applicable micbn_ext_cap setting. the compatible load conditions are detailed in the ?electrical characteristics? section. in bypass mode, the output pin (micbias1, micbias2 or micbias3) is connected directly to micvdd. this enables a low power operating state. note that the micbn_ext_cap register settings are not applicable in bypass mode. the micbias generators incorporate a pop-free control circuit to ensure smooth transitions when the micbias outputs are enabled or disabled in bypa ss mode; this feature is enabled using the micb n _rate registers. the micbias generators are illustrated in figure 77. the micbias control register bits are described in table 111. the maximum output current for each micbias n pin is noted in the ?electrical characteristics?. this limit must be observed on each micbias output, es pecially if more than one microphone is connected to a single micbias pin. note that the maximu m output current differs between regulator mode and bypass mode. voltage reference circuit the WM5102 incorporates a voltage reference circui t, powered by avdd. this circuit ensures the accuracy of the ldo regulator and micbias voltage settings. ldo1 regulator and dcvdd supply the ldo1 voltage regulator is intended for generat ing the dcvdd domain, which powers the digital core functions on the WM5102. ldo1 is powered by ldovdd and can be controlled using hardware or software controls. under hardware control, ldo1 is enabled when a logi c ?1? is applied to the ldoena pin. the logic level is determined with respect to the dbvdd1 voltage domain. ldo1 is also enabled when the ldo1_ena software control register is set to 1. note that, to disable ldo1, the hardware and software controls must both be de-asserted. when ldo1 is enabled, an internal bypass path may be selected, connecting the ldovout pin directly to the ldovdd supply. this path is cont rolled using the ldo1_bypass register. note that the bypass path is only supported when ldo1 is enabled. when ldo1 is disabled, the ld ovout pin can be configured to be floating or to be actively discharged. this is selected usi ng the ldo1_disch register bit. when ldo1 is enabled, the ldovout voltage can be controlled using the ldo1_vsel register. setting ldo1_hi_pwr=1 will override the ldo1_vsel register and select 1.8v ldo output voltage. note that, under default conditions, ldo1_hi_pwr is set to ?1?. it is possible to supply dcvdd from an external supply; separate ldov out and dcvdd pins are provided for flexibility. for recommended use of the sleep / wake-up functions (see ?low power sleep configuration?), it is assumed that dcvdd is powered from the output of ldo1. in this case, sleep mode is selected by setting ldo1_ena=0. the avdd, dbvdd1 and ldovdd supplies must be present, and the ldoena pin held low, allowing the WM5102 registers to control ldo1. if dcvdd is powered externally (not from ldo1), then the isolate_dcvdd1 register bit must be controlled as described in table 111 when select ing WM5102 sleep mode. in this case, only the avdd and dbvdd1 supplies are required in sleep mode. an internal pull-down resistor is enabled by default on the ldoena pin. this is configurable using the ldo1ena_pd register bit.
production data WM5102 w pd, may 2013, rev 4.0 251 the ldo1 regulator circuit is illustrated in figur e 77. the associated register control bits are described in table 111. note that a decoupling capacitor is recommended. refe r to the ?applications information? section for recommended external components. block diagram and control registers the charge pump and regulator circuits are illustra ted in figure 77. note that decoupling capacitors and flyback capacitors are required fo r these circuits. refer to the ?a pplications information? section for recommended external components. vrefc cp1ca cp1voutp cp1voutn cp1cb figure 77 charge pumps and regulators
WM5102 production data w pd, may 2013, rev 4.0 252 register address bit label default description r512 (0200h) mic charge pump 1 2 cp2_disch 1 charge pump 2 discharge 0 = cp2vout floating when disabled 1 = cp2vout discharged when disabled 1 cp2_bypass 1 charge pump 2 and ldo2 bypass mode 0 = normal 1 = bypass mode in bypass mode, cpvdd is connected directly to micvdd. note that cp2_ena must also be set. 0 cp2_ena 0 charge pump 2 and ldo2 control (provides analogue input and micvdd supplies) 0 = disabled 1 = enabled r528 (0210h) ldo1 control 1 10:5 ldo1_vsel [5:0] 0ch ldo1 output voltage select controls the ldo1 output voltage when ldo1_hi_pwr=0. 00h = 0.9v 01h = 0.95v 02h = 1.0v 03h = 1.05v 04h = 1.1v 05h = 1.15v 06h = 1.2v 07h to 3fh = reserved 2 ldo1_disch 1 ldo1 discharge 0 = ldovout floating when disabled 1 = ldovout discharged when disabled 1 ldo1_bypass 0 ldo1 bypass mode 0 = normal 1 = bypass mode in bypass mode, ldovdd is connected directly to ldovout. note that ldo1_ena must also be set. 0 ldo1_ena 0 ldo1 control 0 = disabled 1 = enabled r530 (0212h) ldo1 control 2 0 ldo1_hi_pwr 1 ldo1 output voltage control 0 = set by ldo1_vsel 1 = 1.8v r531 (0213h) ldo2 control 1 10:5 ldo2_vsel [5:0] 1ah ldo2 output voltage select 00h = 1.7v 01h = 1.75v 02h = 1.8v 03h = 1.85v ? (50mv steps) 1dh = 3.15v 1eh = 3.2v 1fh = 3.3v 20h to 3fh = reserved (see table 112 for voltage range) 2 ldo2_disch 1 ldo2 discharge 0 = micvdd floating when disabled 1 = micvdd discharged when disabled
production data WM5102 w pd, may 2013, rev 4.0 253 register address bit label default description r536 (218h) mic bias ctrl 1 15 micb1_ext_ca p 0 microphone bias 1 external capacitor (when micb1_bypass = 0). configures the micbias1 regulator according to the specified capacitance connected to the micbias1 output. 0 = no external capacitor 1 = external capacitor connected 8:5 micb1_lvl [3:0] dh microphone bias 1 voltage control (when micb1_bypass = 0) 0h = 1.5v 1h = 1.6v ? (0.1v steps) dh = 2.8v eh = 2.8v fh = 2.8v 3 micb1_rate 0 microphone bias 1 rate (bypass mode) 0 = fast start-up / shut-down 1 = pop-free start-up / shut-down 2 micb1_disch 1 microphone bias 1 discharge 0 = micbias1 floating when disabled 1 = micbias1 discharged when disabled 1 micb1_bypass 1 microphone bias 1 mode 0 = regulator mode 1 = bypass mode 0 micb1_ena 0 microphone bias 1 enable 0 = disabled 1 = enabled r537 (219h) mic bias ctrl 2 15 micb2_ext_ca p 0 microphone bias 2 external capacitor (when micb2_bypass = 0). configures the micbias2 regulator according to the specified capacitance connected to the micbias2 output. 0 = no external capacitor 1 = external capacitor connected 8:5 micb2_lvl [3:0] dh microphone bias 2 voltage control (when micb2_bypass = 0) 0h = 1.5v 1h = 1.6v ? (0.1v steps) dh = 2.8v eh = 2.8v fh = 2.8v 3 micb2_rate 0 microphone bias 2 rate (bypass mode) 0 = fast start-up / shut-down 1 = pop-free start-up / shut-down 2 micb2_disch 1 microphone bias 2 discharge 0 = micbias2 floating when disabled 1 = micbias2 discharged when disabled 1 micb2_bypass 1 microphone bias 2 mode 0 = regulator mode 1 = bypass mode 0 micb2_ena 0 microphone bias 2 enable 0 = disabled 1 = enabled
WM5102 production data w pd, may 2013, rev 4.0 254 register address bit label default description r538 (21ah) mic bias ctrl 3 15 micb3_ext_ca p 0 microphone bias 3 external capacitor (when micb3_bypass = 0). configures the micbias3 regulator according to the specified capacitance connected to the micbias3 output. 0 = no external capacitor 1 = external capacitor connected 8:5 micb3_lvl [3:0] dh microphone bias 3 voltage control (when micb3_bypass = 0) 0h = 1.5v 1h = 1.6v ? (0.1v steps) dh = 2.8v eh = 2.8v fh = 2.8v 3 micb3_rate 0 microphone bias 3 rate (bypass mode) 0 = fast start-up / shut-down 1 = pop-free start-up / shut-down 2 micb3_disch 1 microphone bias 3 discharge 0 = micbias3 floating when disabled 1 = micbias3 discharged when disabled 1 micb3_bypass 1 microphone bias 3 mode 0 = regulator mode 1 = bypass mode 0 micb3_ena 0 microphone bias 3 enable 0 = disabled 1 = enabled r3104 (0c20h) misc pad ctrl 1 15 ldo1ena_pd 1 ldoena pull-down control 0 = disabled 1 = enabled r715 (02cbh) isolation control 0 isolate_dcvd d1 0 always-on power domain isolate control set this bit to 1 to isolate the ?always-on? domain from the dcvdd pin. if dcvdd is powered externally (not from ldo1), this bit must be set before selecting sleep mode (ie. before removing the external dcvdd supply). if dcvdd is powered from ldo1, then there is no requirement to set this bit. this bit is automatically reset to 0 following a wake-up transition (from sleep mode). table 111 charge pump and ldo control registers
production data WM5102 w pd, may 2013, rev 4.0 255 ldo2_vsel [5:0] ldo2 output ldo2_vsel [5:0] ldo2 output 00h 1.70v 10h 2.50v 01h 1.75v 11h 2.55v 02h 1.80v 12h 2.60v 03h 1.85v 13h 2.65v 04h 1.90v 14h 2.70v 05h 1.95v 15h 2.75v 06h 2.00v 16h 2.80v 07h 2.05v 17h 2.85v 08h 2.10v 18h 2.90v 09h 2.15v 19h 2.95v 0ah 2.20v 1ah 3.00v 0bh 2.25v 1bh 3.05v 0ch 2.30v 1ch 3.10v 0dh 2.35v 1dh 3.15v 0eh 2.40v 1eh 3.20v 0fh 2.45v 1fh 3.30v table 112 ldo2 voltage control
WM5102 production data w pd, may 2013, rev 4.0 256 jtag interface the jtag interface provides test and debug a ccess to the WM5102 dsp core. the interface comprises 5 pins, as detailed below. ? tck: clock input ? tdi: data input ? tdo: data output ? tms: mode select input ? trst: test access port reset input (active low, internal pull-down) for normal operation (test and debug access disabled), t he jtag interface should be held in reset (ie. trst should be at logic 0). an internal pull-down re sistor holds the trst pin low when not actively driven. the other jtag input pins (tck, tdi, tmsdsp) s hould also be held at logic 0 for normal operation. thermal shutdown the WM5102 incorporates a temperature sensor whic h detects when the device temperature is within normal limits or if the device is approac hing a hazardous temperature condition. the temperature sensor is an input to the inte rrupt control circuit and can be used to trigger an interrupt event - see ?interrupts?. the warning temperature and shutdown temperature status flags can be output directly on a gpio pin as an external indication of the temperature sensor. see ?general purpose input / output? to configure a gpio pin for this function. it is strongly recommended that the speaker driv ers be disabled if the shutdown temperature condition occurs. power-on reset (por) the WM5102 will remain in the reset state until avdd, dbvdd1 and dcvdd are all above their respective reset thresholds. note that specified device performance is not assured outside the voltage ranges defined in the ?recommended operating conditions? section. refer to ?recommended operating conditions? fo r the WM5102 power-up sequencing requirements. following power-on reset (por), a boot sequence is executed. the boot_done_sts register is asserted on completion of the boot sequence, as de scribed in table 113. control register writes should not be attempted until the boot_done_sts register has been asserted. the boot_done_sts signal is an input to the inte rrupt control circuit and can be used to trigger an interrupt event - see ?interrupts?. under def ault register conditions, a falling edge on the irq pin will indicate completion of the boot sequence. the boot_done_sts signal can be output directly on a gpio pin as an external indication of the boot sequence. see ?general purpose input / output ? to configure a gpio pin for this function. for details of the boot sequence, see ?control write sequencer?.
production data WM5102 w pd, may 2013, rev 4.0 257 register address bit label default description r3363 (0d23h) interrupt raw status 5 8 boot_done_s ts 0 boot status 0 = busy (boot sequence in progress) 1 = idle (boot sequence completed) control register writes should not be attempted until boot sequence has completed. table 113 device boot-up status the WM5102 is in sleep mode when avdd and dbvdd1 are present, and dcvdd is below its reset threshold. (note that specific control requirements are also app licable for entering sleep mode, as described in ?low power sleep configuration?.) in sleep mode, most of the digital core (and contro l registers) are held in reset; selected functions and control registers are maintained via an ?alway s-on? internal supply domain. see ?low power sleep configuration? for details of the ?always-on? functions. see ?hardware reset, software reset, wake-up, and device id? for details of the wake-up transition (exit from sleep mode). table 114 describes the default status of the wm 5102 digital i/o pins on completion of power-on reset, prior to any register writes. the same def ault conditions are also app licable on completion of a hardware reset or software reset (see ?hardware reset, software reset, wake-up, and device id?). the same default conditions are applicable following a wake-up transition, except for the gpio5, irq, ldoena, mclk2 and reset pins. these are ?always-on? pins whose configuration is unchanged in sleep mode and during a wake-up transition. note that the default conditions described in tabl e 114 will not be valid if modified by the boot sequence or by a ?wake-up? control sequence. see ?control write sequencer? for details of these functions. pin no name type reset status micvdd power domain e3 in1ln / dmicclk1 analogue input / digital output analogue input e1 in1rn / dmicdat1 analogue input / digital input analogue input c1 in2ln / dmicclk2 analogue input / digital output analogue input d1 in2rn / dmicdat2 analogue input / digital input analogue input a1 in3ln / dmicclk3 analogue input / digital output analogue input b1 in3rn / dmicdat3 analogue input / digital input analogue input dbvdd1 power domain j13 aif1bclk digital input / output digital input j11 aif1rxdat digital input digital input j12 aif1lrclk digital input / output digital input j8 aif1txdat digital output digital output l13 cif1addr digital input digital input, pull-down to dgnd k12 cif1sclk digital input digital input k11 cif1sda digital input / output digital input m13 cif2mosi digital input digital input k9 cif2miso digital output digital output l12 cif2sclk digital input digital input l11 cif2ss digital input digital input k13 gpio1 digital input / output digital input, pull-down to dgnd
WM5102 production data w pd, may 2013, rev 4.0 258 pin no name type reset status k10 gpio4 digital input / output digital input, pull-down to dgnd g10 gpio5 digital input / output digital input, pull-down to dgnd f13 irq digital output digital output f11 ldoena digital input digital input, pull-down to dgnd h13 mclk1 digital input digital input f12 mclk2 digital input digital input e13 reset digital input digital input, pull-up to dbvdd1 h12 slimclk digital input / output digital input h11 slimdat digital input / output digital input l10 spkclk digital output digital output k8 spkdat digital output digital output l9 tck digital input digital input m11 tdi digital input digital input k6 tdo digital output digital output k7 tms digital input digital input m12 trst digital input digital input, pull-down to dgnd dbvdd2 power domain k5 aif2bclk digital input / output digital input m9 aif2rxdat digital input digital input l8 aif2lrclk digital input / output digital input l6 aif2txdat digital output digital output l7 gpio2 digital input / output digital input, pull-down to dgnd dbvdd3 power domain l5 aif3bclk digital input / output digital input k4 aif3rxdat digital input digital input m5 aif3lrclk digital input / output digital input l4 aif3txdat digital output digital output k3 gpio3 digital input / output digital input, pull-down to dgnd table 114 WM5102 digital i/o status in reset note that the dual function innln/dmicclkn and inn rn/dmicdatn pins default to their respective analogue input functions after power-on reset is completed. the analogue input functions are referenced to the micvdd power domain.
production data WM5102 w pd, may 2013, rev 4.0 259 hardware reset, software reset, wake-up, and device id the WM5102 provides a hardware reset func tion, which is executed whenever the reset input is asserted (logic 0). the reset input is acti ve low and is referenced to the dbvdd1 power domain. a hardware reset causes most of the WM5102 contro l registers to be reset to their default states. note that the control write sequencer memory and dsp firmware is not affected by hardware reset. an internal pull-up resistor is enabled by default on the reset pin; this can be configured using the reset_pu register bit described in table 115. register address bit label default description r3104 (0c20h) misc pad ctrl 1 1 reset_pu 1 reset pull-up enable 0 = disabled 1 = enabled table 115 reset pull-up configuration a software reset is executed by writing any value to register r0. a software reset causes most of the WM5102 control registers to be reset to their def ault states. note that the control write sequencer memory and dsp firmware memory is not affected by software reset. a wake-up transition (from sleep mode) is simila r to a software reset, but selected functions and control registers are maintained via an ?always-on? internal supply domain. the ?always-on? registers are not reset during wake-up. see ?low power sleep configuration? for details of the ?always-on? functions. the control write sequencer memory is not affected by hardware reset, software reset or sleep mode; these registers are only reset following a power-on reset (por). following hardware reset, software reset or wake-up (from sleep mode), a boot sequence is executed. the boot_done_sts register (see t able 113) is de-asserted during hardware reset, software reset and in sleep mode. the boot_done_st s register is asserted on completion of the boot-up sequence. control register writes should not be attempted until the boot_done_sts register has been asserted. the boot_done_sts signal is an input to the inte rrupt control circuit and can be used to trigger an interrupt event - see ?interrupts?. the boot_done_sts signal can be output directly on a gpio pin as an external indication of the boot sequence. see ?general purpose input / output ? to configure a gpio pin for this function. for details of the boot sequence, see ?control write sequencer?.
WM5102 production data w pd, may 2013, rev 4.0 260 the status of the WM5102 digital i/o pins followi ng hardware reset, software reset or wake-up is described in the ?power-on reset (por)? section. the device id can be read back from register r0 . the revision can be read back from register r1. register address bit label default description r0 (0000h) software reset 15:0 sw_rst_dev_ id [15:0] 5102h writing to this register resets all registers to their default state. reading from this register will indicate device id 5102h. r1 (0001h) device revision 7:0 device_revis ion [7:0] device revision table 116 device reset and id
production data WM5102 w pd, may 2013, rev 4.0 261 register map the WM5102 control registers are listed below. note that only t he register addresses described her e should be accessed; writing to other addresses may result in undefined behaviour. register bits that are not documented should not be changed from the default values. reg name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 default r0 (0h) software reset sw_rst_dev_id [15:0] 5102h r1 (1h) device revision 0 0 0 0 0 0 0 0 device_revision [7:0] r8 (8h) ctrl if spi cfg 1 0 0 0 0 0 0 0 0 0 0 0 spi_c fg 0 0 spi_auto_in c [1:0] 0011h r9 (9h) ctrl if i2c1 cfg 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i2c1_auto_in c [1:0] 0001h r22 (16h) write sequencer ctrl 0 0 0 0 0 wseq _abo rt wseq _star t wseq _ena wseq_start_index [8:0] 0000h r23 (17h) write sequencer ctrl 1 0 0 0 0 0 0 wseq _bus y wseq_current_index [8:0] 0000h r24 (18h) write sequencer ctrl 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 wseq _boo t_sta rt wseq _loa d_me m 0000h r32 (20h) tone generator 1 0 tone_rate [3:0] 0 tone_offse t [1:0] 0 0 tone 2_ov d tone 1_ov d 0 0 tone 2_ena tone 1_ena 0000h r33 (21h) tone generator 2 tone1_lvl [23:8] 1000h r34 (22h) tone generator 3 0 0 0 0 0 0 0 0 tone1_lvl [7:0] 0000h r35 (23h) tone generator 4 tone2_lvl [23:8] 1000h r36 (24h) tone generator 5 0 0 0 0 0 0 0 0 tone2_lvl [7:0] 0000h r48 (30h) pwm drive 1 0 pwm_rate [3:0] pwm_clk_sel [2:0] 0 0 pwm2 _ovd pwm1 _ovd 0 0 pwm2 _ena pwm1 _ena 0000h r49 (31h) pwm drive 2 0 0 0 0 0 0 pwm1_lvl [9:0] 0100h r50 (32h) pwm drive 3 0 0 0 0 0 0 pwm2_lvl [9:0] 0100h r64 (40h) wake control 0 0 0 0 0 0 0 0 wkup _micd _cla mp_f all wkup _micd _cla mp_ri se wkup _gp5_ fall wkup _gp5_ rise wkup _jd1_ fall wkup _jd1_ rise 0 0 0000h r65 (41h) sequence control 0 0 0 0 0 0 0 0 wseq _ena_ micd_ clam p_fal l wseq _ena_ micd_ clam p_ris e wseq _ena_ gp5_f all wseq _ena_ gp5_ rise wseq _ena_ jd1_f all wseq _ena_ jd1_r ise 0 0 0000h r97 (61h) sample rate sequence select 1 0 0 0 0 0 0 0 wseq_sample_rate _detect_a_ind ex [8:0] 01ffh r98 (62h) sample rate sequence select 2 0 0 0 0 0 0 0 wseq_sample_rate _detect_b_ind ex [8:0] 01ffh r99 (63h) sample rate sequence select 3 0 0 0 0 0 0 0 wseq_sample_rate_detect_c_index [8:0] 01ffh r100 (64h) sample rate sequence select 4 0 0 0 0 0 0 0 wseq_sample_rate_detect_d_index [8:0] 01ffh r102 (66h) a lways on triggers sequence select 1 0 0 0 0 0 0 0 wseq_micd_clamp_rise_index [8:0] 01ffh r103 (67h) a lways on triggers sequence select 2 0 0 0 0 0 0 0 wseq_micd_clamp_fall_index [8:0] 01ffh r104 (68h) a lways on triggers sequence select 3 0 0 0 0 0 0 0 wseq_gp5_rise_index [8:0] 01ffh
WM5102 production data w pd, may 2013, rev 4.0 262 reg name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 default r105 (69h) a lways on triggers sequence select 4 0 0 0 0 0 0 0 wseq_gp5_fall_index [8:0] 01ffh r106 (6ah) a lways on triggers sequence select 5 0 0 0 0 0 0 0 wseq_jd1_rise_index [8:0] 01ffh r107 (6bh) a lways on triggers sequence select 6 0 0 0 0 0 0 0 wseq_jd1_fall_index [8:0] 01ffh r110 (6eh) trigger sequence select 32 0 0 0 0 0 0 0 wseq_drc1_sig_det_rise_index [8:0] 01ffh r111 (6fh) trigger sequence select 33 0 0 0 0 0 0 0 wseq_drc1_sig_det_fall_index [8:0] 01ffh r112 (70h) comfort noise generator 0 noise_gen_rate [3:0] 0 0 0 0 0 noise _gen _ena noise_gen_gain [4:0] 0000h r144 (90h) haptics control 1 0 hap_rate [3:0] 0 0 0 0 0 0 ones hot_ trig hap_ctrl [1:0] hap_ act 0 0000h r145 (91h) haptics control 2 0 lra_freq [14:0] 7fffh r146 (92h) haptics phase 1 intensity 0 0 0 0 0 0 0 0 phase1_intensity [7:0] 0000h r147 (93h) haptics phase 1 duration 0 0 0 0 0 0 0 phase1_duration [8:0] 0000h r148 (94h) haptics phase 2 intensity 0 0 0 0 0 0 0 0 phase2_intensity [7:0] 0000h r149 (95h) haptics phase 2 duration 0 0 0 0 0 phase2_duration [10:0] 0000h r150 (96h) haptics phase 3 intensity 0 0 0 0 0 0 0 0 phase3_intensity [7:0] 0000h r151 (97h) haptics phase 3 duration 0 0 0 0 0 0 0 phase3_duration [8:0] 0000h r152 (98h) haptics status 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ones hot_ sts 0000h r256 (100h) clock 32k 1 0 0 0 0 0 0 0 0 0 clk_3 2k_en a 0 0 0 0 clk_32k_src [1:0] 0002h r257 (101h) system clock 1 sysc lk_fr ac 0 0 0 0 sysclk_freq [2:0] 0 sysc lk_en a 0 0 sysclk_src [3:0] 0304h r258 (102h) sample rate 1 0 0 0 0 0 0 0 0 0 0 0 sample_rate_1 [4:0] 0011h r259 (103h) sample rate 2 0 0 0 0 0 0 0 0 0 0 0 sample_rate_2 [4:0] 0011h r260 (104h) sample rate 3 0 0 0 0 0 0 0 0 0 0 0 sample_rate_3 [4:0] 0011h r266 (10ah) sample rate 1 status 0 0 0 0 0 0 0 0 0 0 0 sample_rate_1_sts [4:0] 0000h r267 (10bh) sample rate 2 status 0 0 0 0 0 0 0 0 0 0 0 sample_rate_2_sts [4:0] 0000h r268 (10ch) sample rate 3 status 0 0 0 0 0 0 0 0 0 0 0 sample_rate_3_sts [4:0] 0000h r274 (112h) async clock 1 0 0 0 0 0 async_clk_freq [2:0] 0 asyn c_clk _ena 0 0 async_clk_src [3:0] 0305h r275 (113h) async sample rate 1 0 0 0 0 0 0 0 0 0 0 0 async_sample_rate_1 [4:0] 0011h r276 (114h) async sample rate 2 0 0 0 0 0 0 0 0 0 0 0 async_sample_rate_2 [4:0] 0011h r283 (11bh) async sample rate 1 status 0 0 0 0 0 0 0 0 0 0 0 async_sample_rate_1_sts [4:0] 0000h
production data WM5102 w pd, may 2013, rev 4.0 263 reg name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 default r284 (11bh) async sample rate 2 status 0 0 0 0 0 0 0 0 0 0 0 async_sample_rate_2_sts [4:0] 0000h r329 (149h) output system clock opcl k_en a 0 0 0 0 0 0 0 opclk_div [4:0] opclk_sel [2:0] 0000h r330 (14ah) output async clock opcl k_asy nc_e na 0 0 0 0 0 0 0 opclk_async_div [4:0] opclk_async_sel [2:0] 0000h r338 (152h) rate estimator 1 0 0 0 0 0 0 0 0 0 0 0 trig_ on_s tart up lrclk_src [2:0] rate_ est_e na 0000h r339 (153h) rate estimator 2 0 0 0 0 0 0 0 0 0 0 0 sample_rate_detect_a [4:0] 0000h r340 (154h) rate estimator 3 0 0 0 0 0 0 0 0 0 0 0 sample_rate_detect_b [4:0] 0000h r341 (155h) rate estimator 4 0 0 0 0 0 0 0 0 0 0 0 sample_rate_detect_c [4:0] 0000h r342 (156h) rate estimator 5 0 0 0 0 0 0 0 0 0 0 0 sample_rate_detect_d [4:0] 0000h r353 (161h) dynamic frequency scaling 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 subs ys_m ax_fr eq 0000h r369 (171h) fll1 control 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 fll1_ free run fll1_ ena 0002h r370 (172h) fll1 control 2 fll1_ ctrl_ upd 0 0 0 0 0 fll1_n [9:0] 0008h r371 (173h) fll1 control 3 fll1_theta [15:0] 0018h r372 (174h) fll1 control 4 fll1_lambda [15:0] 007dh r373 (175h) fll1 control 5 0 0 0 0 0 fll1_fratio [2:0] 0 0 0 0 fll1_outdiv [2:0] 0 0004h r374 (176h) fll1 control 6 0 0 0 0 0 0 0 0 fll1_refclk _div [1:0] 0 0 fll1_refclk_src [3:0] 0000h r377 (179h) fll1 control 7 0 0 0 0 0 0 0 0 0 0 fll1_gain [3:0] 0 0 0000h r385 (181h) fll1 synchroniser 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 fll1_ sync _ena 0000h r386 (182h) fll1 synchroniser 2 0 0 0 0 0 0 fll1_sync_n [9:0] 0000h r387 (183h) fll1 synchroniser 3 fll1_sync_theta [15:0] 0000h r388 (184h) fll1 synchroniser 4 fll1_sync_lambda [15:0] 0000h r389 (185h) fll1 synchroniser 5 0 0 0 0 0 fll1_sync_fratio [2:0] 0 0 0 0 0 0 0 0 0000h r390 (186h) fll1 synchroniser 6 0 0 0 0 0 0 0 0 fll1_synccl k_div [1:0] 0 0 fll1_syncclk_src [3:0] 0000h r391 (187h) fll1 synchroniser 7 0 0 0 0 0 0 0 0 0 0 fll1_sync_gain [3:0] 0 fll1_ sync _dfsa t 0001h r393 (189h) fll1 spread spectrum 0 0 0 0 0 0 0 0 0 0 fll1_ss_amp l [1:0] fll1_ss_fre q [1:0] fll1_ss_sel [1:0] 0000h r394 (18ah) fll1 gpio clock 0 0 0 0 0 0 0 0 fll1_gpclk_div [6:0] fll1_ gpcl k_en a 0004h
WM5102 production data w pd, may 2013, rev 4.0 264 reg name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 default r401 (191h) fll2 control 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 fll2_ free run fll2_ ena 0000h r402 (192h) fll2 control 2 fll2_ ctrl_ upd 0 0 0 0 0 fll2_n [9:0] 0008h r403 (193h) fll2 control 3 fll2_theta [15:0] 0018h r404 (194h) fll2 control 4 fll2_lambda [15:0] 007dh r405 (195h) fll2 control 5 0 0 0 0 0 fll2_fratio [2:0] 0 0 0 0 fll2_outdiv [2:0] 0 0004h r406 (196h) fll2 control 6 0 0 0 0 0 0 0 0 fll2_refclk _div [1:0] 0 0 fll2_refclk_src [3:0] 0000h r409 (199h) fll2 control 7 0 0 0 0 0 0 0 0 0 0 fll2_gain [3:0] 0 0 0000h r417 (1a1h) fll2 synchroniser 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 fll2_ sync _ena 0000h r418 (1a2h) fll2 synchroniser 2 0 0 0 0 0 0 fll2_sync_n [9:0] 0000h r419 (1a3h) fll2 synchroniser 3 fll2_sync_theta [15:0] 0000h r420 (1a4h) fll2 synchroniser 4 fll2_sync_lambda [15:0] 0000h r421 (1a5h) fll2 synchroniser 5 0 0 0 0 0 fll2_sync_fratio [2:0] 0 0 0 0 0 0 0 0 0000h r422 (1a6h) fll2 synchroniser 6 0 0 0 0 0 0 0 0 fll2_synccl k_div [1:0] 0 0 fll2_syncclk_src [3:0] 0000h r423 (1a7h) fll2 synchroniser 7 0 0 0 0 0 0 0 0 0 0 fll2_sync_gain [3:0] 0 fll2_ sync _dfsa t 0001h r425 (1a9h) fll2 spread spectrum 0 0 0 0 0 0 0 0 0 0 fll2_ss_amp l [1:0] fll2_ss_fre q [1:0] fll2_ss_sel [1:0] 0000h r426 (1aah) fll2 gpio clock 0 0 0 0 0 0 0 0 fll2_gpclk_div [6:0] fll2_ gpcl k_en a 0004h r512 (200h) mic charge pump 1 0 0 0 0 0 0 0 0 0 0 0 0 0 cp2_d isch cp2_b ypas s cp2_e na 0006h r528 (210h) ldo1 control 1 0 0 0 0 0 ldo1_vsel [5:0] 0 0 ldo1_ disch ldo1_ bypa ss ldo1_ ena 00d4h r530 (212h) ldo1 control 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ldo1_ hi_pw r 0001h r531 (213h) ldo2 control 1 0 0 0 0 0 ldo2_vsel [5:0] 0 0 ldo2_ disch 0 0 0344h r536 (218h) mic bias ctrl 1 micb1 _ext_ cap 0 0 0 0 0 0 micb1_lvl [3:0] 0 micb1 _rate micb1 _disc h micb1 _bypa ss micb1 _ena 01a6h r537 (219h) mic bias ctrl 2 micb2 _ext_ cap 0 0 0 0 0 0 micb2_lvl [3:0] 0 micb2 _rate micb2 _disc h micb2 _bypa ss micb2 _ena 01a6h r538 (21ah) mic bias ctrl 3 micb3 _ext_ cap 0 0 0 0 0 0 micb3_lvl [3:0] 0 micb3 _rate micb3 _disc h micb3 _bypa ss micb3 _ena 01a6h r659 (293h) accessory detect mode 1 0 0 accd et_sr c 0 0 0 0 0 0 0 0 0 0 0 accdet_mod e [1:0] 0000h
production data WM5102 w pd, may 2013, rev 4.0 265 reg name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 default r667 (29bh) headphone detect 1 0 0 0 0 0 hp_impedan ce_range [1:0] 0 hp_holdtime [2:0] 0 0 0 hp_r ate hp_p oll 0020h r668 (29ch) headphone detect 2 hp_d one hp_lvl [14:0] 0000h r674 (2a2h) micd clamp control 0 0 0 0 0 0 0 0 0 0 0 0 micd_clamp_mode [3:0] 0000h r675 (2a3h) mic detect 1 micd_bias_starttime [3:0] micd_rate [3:0] 0 0 micd_bias_s rc [1:0] 0 0 micd_ dbtim e micd_ ena 1102h r676 (2a4h) mic detect 2 0 0 0 0 0 0 0 0 micd_lvl_sel [7:0] 009fh r677 (2a5h) mic detect 3 0 0 0 0 0 micd_lvl [8:0] micd_ valid micd_ sts 0000h r707 (2c3h) mic noise mix control 1 0 micmute_rate [3:0] 0 0 0 micm ute_ noise _ena micm ute_ mix_e na 0 0 0 0 0 0 0000h r715 (2cbh) isolation control 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 isola te_d cvdd 1 0000h r723 (2d3h) jack detect analogue 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 jd1_e na 0000h r768 (300h) input enables 0 0 0 0 0 0 0 0 0 0 in3l_ ena in3r_ ena in2l_ ena in2r_ ena in1l_ ena in1r_ ena 0000h r769 (301h) input enables status 0 0 0 0 0 0 0 0 0 0 in3l_ ena_ sts in3r_ ena_ sts in2l_ ena_ sts in2r_ ena_ sts in1l_ ena_ sts in1r_ ena_ sts 0000h r776 (308h) input rate 0 in_rate [3:0] 0 0 0 0 0 0 0 0 0 0 0 0000h r777 (309h) input volume ramp 0 0 0 0 0 0 0 0 0 in_vd_ramp [2:0] 0 in_vi_ramp [2:0] 0022h r784 (310h) in1l control 0 in1_osr [1:0] in1_dmic_su p [1:0] in1_mode [1:0] 0 in1l_pga_vol [6:0] 0 2080h r785 (311h) adc digital volume 1l 0 0 0 0 0 0 in_vu in1l_ mute in1l_vol [7:0] 0180h r786 (312h) dmic1l control 0 0 0 0 0 0 0 0 0 0 in1_dmicl_dly [5:0] 0000h r788 (314h) in1r control 0 0 0 0 0 0 0 0 in1r_pga_vol [6:0] 0 0080h r789 (315h) adc digital volume 1r 0 0 0 0 0 0 in_vu in1r_ mute in1r_vol [7:0] 0180h r790 (316h) dmic1r control 0 0 0 0 0 0 0 0 0 0 in1_dmicr_dly [5:0] 0000h r792 (318h) in2l control 0 in2_osr [1:0] in2_dmic_su p [1:0] in2_mode [1:0] 0 in2l_pga_vol [6:0] 0 2080h r793 (319h) adc digital volume 2l 0 0 0 0 0 0 in_vu in2l_ mute in2l_vol [7:0] 0180h r794 (31ah) dmic2l control 0 0 0 0 0 0 0 0 0 0 in2_dmicl_dly [5:0] 0000h r796 (31ch) in2r control 0 0 0 0 0 0 0 0 in2r_pga_vol [6:0] 0 0080h r797 (31dh) adc digital volume 2r 0 0 0 0 0 0 in_vu in2r_ mute in2r_vol [7:0] 0180h r798 (31eh) dmic2r control 0 0 0 0 0 0 0 0 0 0 in2_dmicr_dly [5:0] 0000h r800 (320h) in3l control 0 in3_osr [1:0] in3_dmic_su p [1:0] in3_mode [1:0] 0 in3l_pga_vol [6:0] 0 2080h r801 (321h) adc digital volume 3l 0 0 0 0 0 0 in_vu in3l_ mute in3l_vol [7:0] 0180h r802 (322h) dmic3l control 0 0 0 0 0 0 0 0 0 0 in3_dmicl_dly [5:0] 0000h r804 (324h) in3r control 0 0 0 0 0 0 0 0 in3r_pga_vol [6:0] 0 0080h r805 (325h) adc digital volume 3r 0 0 0 0 0 0 in_vu in3r_ mute in3r_vol [7:0] 0180h
WM5102 production data w pd, may 2013, rev 4.0 266 reg name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 default r806 (326h) dmic3r control 0 0 0 0 0 0 0 0 0 0 in3_dmicr_dly [5:0] 0000h r1024 (400h) output enables 1 0 0 0 0 0 0 out5l _ena out5 r_en a out4l _ena out4 r_en a ep_e na 0 hp2l_ ena hp2r_ ena hp1l_ ena hp1r_ ena 0000h r1025 (401h) output status 1 0 0 0 0 0 0 out5l _ena_ sts out5 r_en a_sts out4l _ena_ sts out4 r_en a_sts 0 0 0 0 0 0 0000h r1030 (406h) raw output status 1 0 0 0 0 0 0 0 0 0 0 out3_ ena_ sts 0 out2l _ena_ sts out2 r_en a_sts out1l _ena_ sts out1 r_en a_sts 0000h r1032 (408h) output rate 1 0 out_rate [3:0] 0 0 0 0 0 0 0 0 0 0 0 0000h r1033 (409h) output volume ramp 0 0 0 0 0 0 0 0 0 out_vd_ramp [2:0] 0 out_vi_ramp [2:0] 0022h r1040 (410h) output path config 1l 0 0 0 out1_ mono 0 0 0 0 1 0 0 0 0 0 0 0 0080h r1041 (411h) dac digital volume 1l 0 0 0 0 0 0 out_ vu out1l _mut e out1l_vol [7:0] 0180h r1042 (412h) dac volume limit 1l 0 0 0 0 0 0 0 0 out1l_vol_lim [7:0] 0081h r1043 (413h) noise gate select 1l 0 0 0 0 out1l_ngate_src [11:0] 0001h r1044 (414h) output path config 1r 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0080h r1045 (415h) dac digital volume 1r 0 0 0 0 0 0 out_ vu out1 r_mu te out1r_vol [7:0] 0180h r1046 (416h) dac volume limit 1r 0 0 0 0 0 0 0 0 out1r_vol_lim [7:0] 0081h r1047 (417h) noise gate select 1r 0 0 0 0 out1r_ngate_src [11:0] 0002h r1048 (418h) output path config 2l 0 0 0 out2_ mono 0 0 0 0 1 0 0 0 0 0 0 0 0080h r1049 (419h) dac digital volume 2l 0 0 0 0 0 0 out_ vu out2l _mut e out2l_vol [7:0] 0180h r1050 (41ah) dac volume limit 2l 0 0 0 0 0 0 0 0 out2l_vol_lim [7:0] 0081h r1051 (41bh) noise gate select 2l 0 0 0 0 out2l_ngate_src [11:0] 0004h r1052 (41ch) output path config 2r 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0080h r1053 (41dh) dac digital volume 2r 0 0 0 0 0 0 out_ vu out2 r_mu te out2r_vol [7:0] 0180h r1054 (41eh) dac volume limit 2r 0 0 0 0 0 0 0 0 out2r_vol_lim [7:0] 0081h r1055 (41fh) noise gate select 2r 0 0 0 0 out2r_ngate_src [11:0] 0008h r1056 (420h) output path config 3l 0 0 0 out3_ mono 0 0 0 0 1 0 0 0 0 0 0 0 0080h r1057 (421h) dac digital volume 3l 0 0 0 0 0 0 out_ vu out3_ mute out3_vol [7:0] 0180h r1058 (422h) dac volume limit 3l 0 0 0 0 0 0 0 0 out3_vol_lim [7:0] 0081h r1059 (423h) noise gate select 3l 0 0 0 0 out3_ngate_src [11:0] 0010h
production data WM5102 w pd, may 2013, rev 4.0 267 reg name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 default r1064 (428h) output path config 4l 0 0 out4_ osr 0 0 0 0 0 0 0 0 0 0 0 0 0 0000h r1065 (429h) dac digital volume 4l 0 0 0 0 0 0 out_ vu out4l _mut e out4l_vol [7:0] 0180h r1066 (42ah) out volume 4l 0 0 0 0 0 0 0 0 out4l_vol_lim [7:0] 0081h r1067 (42bh) noise gate select 4l 0 0 0 0 out4l_ngate_src [11:0] 0040h r1069 (42dh) dac digital volume 4r 0 0 0 0 0 0 out_ vu out4 r_mu te out4r_vol [7:0] 0180h r1070 (42eh) out volume 4r 0 0 0 0 0 0 0 0 out4r_vol_lim [7:0] 0081h r1071 (42fh) noise gate select 4r 0 0 0 0 out4r_ngate_src [11:0] 0080h r1072 (430h) output path config 5l 0 0 out5_ osr 0 0 0 0 0 0 0 0 0 0 0 0 0 0000h r1073 (431h) dac digital volume 5l 0 0 0 0 0 0 out_ vu out5l _mut e out5l_vol [7:0] 0180h r1074 (432h) dac volume limit 5l 0 0 0 0 0 0 0 0 out5l_vol_lim [7:0] 0081h r1075 (433h) noise gate select 5l 0 0 0 0 out5l_ngate_src [11:0] 0100h r1077 (435h) dac digital volume 5r 0 0 0 0 0 0 out_ vu out5 r_mu te out5r_vol [7:0] 0180h r1078 (436h) dac volume limit 5r 0 0 0 0 0 0 0 0 out5r_vol_lim [7:0] 0081h r1079 (437h) noise gate select 5r 0 0 0 0 out5r_ngate_src [11:0] 0200h r1104 (450h) dac aec control 1 0 0 0 0 0 0 0 0 0 0 aec_loopback_src [3:0] aec_ ena_ sts aec_l oopb ack_ ena 0000h r1112 (458h) noise gate control 0 0 0 0 0 0 0 0 0 0 ngate_hold [1:0] ngate_thr [2:0] ngat e_en a 0001h r1168 (490h) pdm spk1 ctrl 1 0 0 spk1 r_mu te spk1l _mut e 0 0 0 spk1_ mute _endi an spk1_mute_seq [7:0] 0069h r1169 (491h) pdm spk1 ctrl 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 spk1_ fmt 0000h r1280 (500h) aif1 bclk ctrl 0 0 0 0 0 0 0 0 aif1_ bclk_ inv aif1_ bclk_ frc aif1_ bclk_ mstr aif1_bclk_freq [4:0] 000ch r1281 (501h) aif1 tx pin ctrl 0 0 0 0 0 0 0 0 0 0 aif1t x_dat _tri 0 aif1t x_lrc lk_sr c aif1t x_lrc lk_in v aif1t x_lrc lk_fr c aif1t x_lrc lk_m str 0008h r1282 (502h) aif1 rx pin ctrl 0 0 0 0 0 0 0 0 0 0 0 0 0 aif1r x_lrc lk_in v aif1r x_lrc lk_fr c aif1r x_lrc lk_m str 0000h r1283 (503h) aif1 rate ctrl 0 aif1_rate [3:0] 0 0 0 0 aif1_ tri 0 0 0 0 0 0 0000h r1284 (504h) aif1 format 0 0 0 0 0 0 0 0 0 0 0 0 0 aif1_fmt [2:0] 0000h
WM5102 production data w pd, may 2013, rev 4.0 268 reg name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 default r1285 (505h) aif1 tx bclk rate 0 0 0 aif1tx_bcpf [12:0] 0040h r1286 (506h) aif1 rx bclk rate 0 0 0 aif1rx_bcpf [12:0] 0040h r1287 (507h) aif1 frame ctrl 1 0 0 aif1tx_wl [5:0] aif1tx_slot_len [7:0] 1818h r1288 (508h) aif1 frame ctrl 2 0 0 aif1rx_wl [5:0] aif1rx_slot_len [7:0] 1818h r1289 (509h) aif1 frame ctrl 3 0 0 0 0 0 0 0 0 0 0 aif1tx1_slot [5:0] 0000h r1290 (50ah) aif1 frame ctrl 4 0 0 0 0 0 0 0 0 0 0 aif1tx2_slot [5:0] 0001h r1291 (50bh) aif1 frame ctrl 5 0 0 0 0 0 0 0 0 0 0 aif1tx3_slot [5:0] 0002h r1292 (50ch) aif1 frame ctrl 6 0 0 0 0 0 0 0 0 0 0 aif1tx4_slot [5:0] 0003h r1293 (50dh) aif1 frame ctrl 7 0 0 0 0 0 0 0 0 0 0 aif1tx5_slot [5:0] 0004h r1294 (50eh) aif1 frame ctrl 8 0 0 0 0 0 0 0 0 0 0 aif1tx6_slot [5:0] 0005h r1295 (50fh) aif1 frame ctrl 9 0 0 0 0 0 0 0 0 0 0 aif1tx7_slot [5:0] 0006h r1296 (510h) aif1 frame ctrl 10 0 0 0 0 0 0 0 0 0 0 aif1tx8_slot [5:0] 0007h r1297 (511h) aif1 frame ctrl 11 0 0 0 0 0 0 0 0 0 0 aif1rx1_slot [5:0] 0000h r1298 (512h) aif1 frame ctrl 12 0 0 0 0 0 0 0 0 0 0 aif1rx2_slot [5:0] 0001h r1299 (513h) aif1 frame ctrl 13 0 0 0 0 0 0 0 0 0 0 aif1rx3_slot [5:0] 0002h r1300 (514h) aif1 frame ctrl 14 0 0 0 0 0 0 0 0 0 0 aif1rx4_slot [5:0] 0003h r1301 (515h) aif1 frame ctrl 15 0 0 0 0 0 0 0 0 0 0 aif1rx5_slot [5:0] 0004h r1302 (516h) aif1 frame ctrl 16 0 0 0 0 0 0 0 0 0 0 aif1rx6_slot [5:0] 0005h r1303 (517h) aif1 frame ctrl 17 0 0 0 0 0 0 0 0 0 0 aif1rx7_slot [5:0] 0006h r1304 (518h) aif1 frame ctrl 18 0 0 0 0 0 0 0 0 0 0 aif1rx8_slot [5:0] 0007h r1305 (519h) aif1 tx enables 0 0 0 0 0 0 0 0 aif1t x8_en a aif1t x7_en a aif1t x6_en a aif1t x5_en a aif1t x4_en a aif1t x3_en a aif1t x2_en a aif1t x1_en a 0000h r1306 (51ah) aif1 rx enables 0 0 0 0 0 0 0 0 aif1r x8_en a aif1r x7_en a aif1r x6_en a aif1r x5_en a aif1r x4_en a aif1r x3_en a aif1r x2_en a aif1r x1_en a 0000h r1344 (540h) aif2 bclk ctrl 0 0 0 0 0 0 0 0 aif2_ bclk_ inv aif2_ bclk_ frc aif2_ bclk_ mstr aif2_bclk_freq [4:0] 000ch r1345 (541h) aif2 tx pin ctrl 0 0 0 0 0 0 0 0 0 0 aif2t x_dat _tri 0 aif2t x_lrc lk_sr c aif2t x_lrc lk_in v aif2t x_lrc lk_fr c aif2t x_lrc lk_m str 0008h r1346 (542h) aif2 rx pin ctrl 0 0 0 0 0 0 0 0 0 0 0 0 0 aif2r x_lrc lk_in v aif2r x_lrc lk_fr c aif2r x_lrc lk_m str 0000h r1347 (543h) aif2 rate ctrl 0 aif2_rate [3:0] 0 0 0 0 aif2_ tri 0 0 0 0 0 0 0000h r1348 (544h) aif2 format 0 0 0 0 0 0 0 0 0 0 0 0 0 aif2_fmt [2:0] 0000h r1349 (545h) aif2 tx bclk rate 0 0 0 aif2tx_bcpf [12:0] 0040h r1350 (546h) aif2 rx bclk rate 0 0 0 aif2rx_bcpf [12:0] 0040h r1351 (547h) aif2 frame ctrl 1 0 0 aif2tx_wl [5:0] aif2tx_slot_len [7:0] 1818h r1352 (548h) aif2 frame ctrl 2 0 0 aif2rx_wl [5:0] aif2rx_slot_len [7:0] 1818h r1353 (549h) aif2 frame ctrl 3 0 0 0 0 0 0 0 0 0 0 aif2tx1_slot [5:0] 0000h r1354 (54ah) aif2 frame ctrl 4 0 0 0 0 0 0 0 0 0 0 aif2tx2_slot [5:0] 0001h r1361 (551h) aif2 frame ctrl 11 0 0 0 0 0 0 0 0 0 0 aif2rx1_slot [5:0] 0000h r1362 (552h) aif2 frame ctrl 12 0 0 0 0 0 0 0 0 0 0 aif2rx2_slot [5:0] 0001h r1369 (559h) aif2 tx enables 0 0 0 0 0 0 0 0 0 0 0 0 0 0 aif2t x2_en a aif2t x1_en a 0000h
production data WM5102 w pd, may 2013, rev 4.0 269 reg name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 default r1370 (55ah) aif2 rx enables 0 0 0 0 0 0 0 0 0 0 0 0 0 0 aif2r x2_en a aif2r x1_en a 0000h r1408 (580h) aif3 bclk ctrl 0 0 0 0 0 0 0 0 aif3_ bclk_ inv aif3_ bclk_ frc aif3_ bclk_ mstr aif3_bclk_freq [4:0] 000ch r1409 (581h) aif3 tx pin ctrl 0 0 0 0 0 0 0 0 0 0 aif3t x_dat _tri 0 aif3t x_lrc lk_sr c aif3t x_lrc lk_in v aif3t x_lrc lk_fr c aif3t x_lrc lk_m str 0008h r1410 (582h) aif3 rx pin ctrl 0 0 0 0 0 0 0 0 0 0 0 0 0 aif3r x_lrc lk_in v aif3r x_lrc lk_fr c aif3r x_lrc lk_m str 0000h r1411 (583h) aif3 rate ctrl 0 aif3_rate [3:0] 0 0 0 0 aif3_ tri 0 0 0 0 0 0 0000h r1412 (584h) aif3 format 0 0 0 0 0 0 0 0 0 0 0 0 0 aif3_fmt [2:0] 0000h r1413 (585h) aif3 tx bclk rate 0 0 0 aif3tx_bcpf [12:0] 0040h r1414 (586h) aif3 rx bclk rate 0 0 0 aif3rx_bcpf [12:0] 0040h r1415 (587h) aif3 frame ctrl 1 0 0 aif3tx_wl [5:0] aif3tx_slot_len [7:0] 1818h r1416 (588h) aif3 frame ctrl 2 0 0 aif3rx_wl [5:0] aif3rx_slot_len [7:0] 1818h r1417 (589h) aif3 frame ctrl 3 0 0 0 0 0 0 0 0 0 0 aif3tx1_slot [5:0] 0000h r1418 (58ah) aif3 frame ctrl 4 0 0 0 0 0 0 0 0 0 0 aif3tx2_slot [5:0] 0001h r1425 (591h) aif3 frame ctrl 11 0 0 0 0 0 0 0 0 0 0 aif3rx1_slot [5:0] 0000h r1426 (592h) aif3 frame ctrl 12 0 0 0 0 0 0 0 0 0 0 aif3rx2_slot [5:0] 0001h r1433 (599h) aif3 tx enables 0 0 0 0 0 0 0 0 0 0 0 0 0 0 aif3t x2_en a aif3t x1_en a 0000h r1434 (59ah) aif3 rx enables 0 0 0 0 0 0 0 0 0 0 0 0 0 0 aif3r x2_en a aif3r x1_en a 0000h r1507 (5e3h) slimbus framer ref gear 0 0 0 0 0 0 0 0 0 0 0 slimc lk_sr c slimclk_ref_gear [3:0] 0004h r1509 (5e5h) slimbus rates 1 0 slimrx2_rate [3:0] 0 0 0 0 slimrx1_rate [3:0] 0 0 0 0000h r1510 (5e6h) slimbus rates 2 0 slimrx4_rate [3:0] 0 0 0 0 slimrx3_rate [3:0] 0 0 0 0000h r1511 (5e7h) slimbus rates 3 0 slimrx6_rate [3:0] 0 0 0 0 slimrx5_rate [3:0] 0 0 0 0000h r1512 (5e8h) slimbus rates 4 0 slimrx8_rate [3:0] 0 0 0 0 slimrx7_rate [3:0] 0 0 0 0000h r1513 (5e9h) slimbus rates 5 0 slimtx2_rate [3:0] 0 0 0 0 slimtx1_rate [3:0] 0 0 0 0000h r1514 (5eah) slimbus rates 6 0 slimtx4_rate [3:0] 0 0 0 0 slimtx3_rate [3:0] 0 0 0 0000h r1515 (5ebh) slimbus rates 7 0 slimtx6_rate [3:0] 0 0 0 0 slimtx5_rate [3:0] 0 0 0 0000h r1516 (5ech) slimbus rates 8 0 slimtx8_rate [3:0] 0 0 0 0 slimtx7_rate [3:0] 0 0 0 0000h r1525 (5f5h) slimbus rx channel enable 0 0 0 0 0 0 0 0 slimr x8_en a slimr x7_en a slimr x6_en a slimr x5_en a slimr x4_en a slimr x3_en a slimr x2_en a slimr x1_en a 0000h r1526 (5f6h) slimbus tx channel enable 0 0 0 0 0 0 0 0 slimt x8_en a slimt x7_en a slimt x6_en a slimt x5_en a slimt x4_en a slimt x3_en a slimt x2_en a slimt x1_en a 0000h r1527 (5f7h) slimbus rx port status 0 0 0 0 0 0 0 0 slimr x8_po rt_st s slimr x7_po rt_st s slimr x6_po rt_st s slimr x5_po rt_st s slimr x4_po rt_st s slimr x3_po rt_st s slimr x2_po rt_st s slimr x1_po rt_st s 0000h
WM5102 production data w pd, may 2013, rev 4.0 270 reg name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 default r1528 (5f8h) slimbus tx port status 0 0 0 0 0 0 0 0 slimt x8_po rt_st s slimt x7_po rt_st s slimt x6_po rt_st s slimt x5_po rt_st s slimt x4_po rt_st s slimt x3_po rt_st s slimt x2_po rt_st s slimt x1_po rt_st s 0000h r1600 (640h) pwm1mix input 1 source pwm1 mix_s ts1 0 0 0 0 0 0 0 pwm1mix_src1 [7:0] 0000h r1601 (641h) pwm1mix input 1 volume 0 0 0 0 0 0 0 0 pwm1mix_vol1 [6:0] 0 0080h r1602 (642h) pwm1mix input 2 source pwm1 mix_s ts2 0 0 0 0 0 0 0 pwm1mix_src2 [7:0] 0000h r1603 (643h) pwm1mix input 2 volume 0 0 0 0 0 0 0 0 pwm1mix_vol2 [6:0] 0 0080h r1604 (644h) pwm1mix input 3 source pwm1 mix_s ts3 0 0 0 0 0 0 0 pwm1mix_src3 [7:0] 0000h r1605 (645h) pwm1mix input 3 volume 0 0 0 0 0 0 0 0 pwm1mix_vol3 [6:0] 0 0080h r1606 (646h) pwm1mix input 4 source pwm1 mix_s ts4 0 0 0 0 0 0 0 pwm1mix_src4 [7:0] 0000h r1607 (647h) pwm1mix input 4 volume 0 0 0 0 0 0 0 0 pwm1mix_vol4 [6:0] 0 0080h r1608 (648h) pwm2mix input 1 source pwm2 mix_s ts1 0 0 0 0 0 0 0 pwm2mix_src1 [7:0] 0000h r1609 (649h) pwm2mix input 1 volume 0 0 0 0 0 0 0 0 pwm2mix_vol1 [6:0] 0 0080h r1610 (64ah) pwm2mix input 2 source pwm2 mix_s ts2 0 0 0 0 0 0 0 pwm2mix_src2 [7:0] 0000h r1611 (64bh) pwm2mix input 2 volume 0 0 0 0 0 0 0 0 pwm2mix_vol2 [6:0] 0 0080h r1612 (64ch) pwm2mix input 3 source pwm2 mix_s ts3 0 0 0 0 0 0 0 pwm2mix_src3 [7:0] 0000h r1613 (64dh) pwm2mix input 3 volume 0 0 0 0 0 0 0 0 pwm2mix_vol3 [6:0] 0 0080h r1614 (64eh) pwm2mix input 4 source pwm2 mix_s ts4 0 0 0 0 0 0 0 pwm2mix_src4 [7:0] 0000h r1615 (64fh) pwm2mix input 4 volume 0 0 0 0 0 0 0 0 pwm2mix_vol4 [6:0] 0 0080h r1632 (660h) micmix input 1 source micmi x_sts 1 0 0 0 0 0 0 0 micmix_src1 [7:0] 0000h r1633 (661h) micmix input 1 volume 0 0 0 0 0 0 0 0 micmix_vol1 [6:0] 0 0080h r1634 (662h) micmix input 2 source micmi x_sts 2 0 0 0 0 0 0 0 micmix_src2 [7:0] 0000h r1635 (663h) micmix input 2 volume 0 0 0 0 0 0 0 0 micmix_vol2 [6:0] 0 0080h r1636 (664h) micmix input 3 source micmi x_sts 3 0 0 0 0 0 0 0 micmix_src3 [7:0] 0000h r1637 (665h) micmix input 3 volume 0 0 0 0 0 0 0 0 micmix_vol3 [6:0] 0 0080h
production data WM5102 w pd, may 2013, rev 4.0 271 reg name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 default r1638 (666h) micmix input 4 source micmi x_sts 4 0 0 0 0 0 0 0 micmix_src4 [7:0] 0000h r1639 (667h) micmix input 4 volume 0 0 0 0 0 0 0 0 micmix_vol4 [6:0] 0 0080h r1640 (668h) noisemix input 1 source noise mix_s ts1 0 0 0 0 0 0 0 noisemix_src1 [7:0] 0000h r1641 (669h) noisemix input 1 volume 0 0 0 0 0 0 0 0 noisemix_vol1 [6:0] 0 0080h r1642 (66ah) noisemix input 2 source noise mix_s ts2 0 0 0 0 0 0 0 noisemix_src2 [7:0] 0000h r1643 (66bh) noisemix input 2 volume 0 0 0 0 0 0 0 0 noisemix_vol2 [6:0] 0 0080h r1644 (66ch) noisemix input 3 source noise mix_s ts3 0 0 0 0 0 0 0 noisemix_src3 [7:0] 0000h r1645 (66dh) noisemix input 3 volume 0 0 0 0 0 0 0 0 noisemix_vol3 [6:0] 0 0080h r1646 (66eh) noisemix input 4 source noise mix_s ts4 0 0 0 0 0 0 0 noisemix_src4 [7:0] 0000h r1647 (66fh) noisemix input 4 volume 0 0 0 0 0 0 0 0 noisemix_vol4 [6:0] 0 0080h r1664 (680h) out1lmix input 1 source out1l mix_s ts1 0 0 0 0 0 0 0 out1lmix_src1 [7:0] 0000h r1665 (681h) out1lmix input 1 volume 0 0 0 0 0 0 0 0 out1lmix_vol1 [6:0] 0 0080h r1666 (682h) out1lmix input 2 source out1l mix_s ts2 0 0 0 0 0 0 0 out1lmix_src2 [7:0] 0000h r1667 (683h) out1lmix input 2 volume 0 0 0 0 0 0 0 0 out1lmix_vol2 [6:0] 0 0080h r1668 (684h) out1lmix input 3 source out1l mix_s ts3 0 0 0 0 0 0 0 out1lmix_src3 [7:0] 0000h r1669 (685h) out1lmix input 3 volume 0 0 0 0 0 0 0 0 out1lmix_vol3 [6:0] 0 0080h r1670 (686h) out1lmix input 4 source out1l mix_s ts4 0 0 0 0 0 0 0 out1lmix_src4 [7:0] 0000h r1671 (687h) out1lmix input 4 volume 0 0 0 0 0 0 0 0 out1lmix_vol4 [6:0] 0 0080h r1672 (688h) out1rmix input 1 source out1 rmix_ sts1 0 0 0 0 0 0 0 out1rmix_src1 [7:0] 0000h r1673 (689h) out1rmix input 1 volume 0 0 0 0 0 0 0 0 out1rmix_vol1 [6:0] 0 0080h r1674 (68ah) out1rmix input 2 source out1 rmix_ sts2 0 0 0 0 0 0 0 out1rmix_src2 [7:0] 0000h r1675 (68bh) out1rmix input 2 volume 0 0 0 0 0 0 0 0 out1rmix_vol2 [6:0] 0 0080h r1676 (68ch) out1rmix input 3 source out1 rmix_ sts3 0 0 0 0 0 0 0 out1rmix_src3 [7:0] 0000h
WM5102 production data w pd, may 2013, rev 4.0 272 reg name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 default r1677 (68dh) out1rmix input 3 volume 0 0 0 0 0 0 0 0 out1rmix_vol3 [6:0] 0 0080h r1678 (68eh) out1rmix input 4 source out1 rmix_ sts4 0 0 0 0 0 0 0 out1rmix_src4 [7:0] 0000h r1679 (68fh) out1rmix input 4 volume 0 0 0 0 0 0 0 0 out1rmix_vol4 [6:0] 0 0080h r1680 (690h) out2lmix input 1 source out2l mix_s ts1 0 0 0 0 0 0 0 out2lmix_src1 [7:0] 0000h r1681 (691h) out2lmix input 1 volume 0 0 0 0 0 0 0 0 out2lmix_vol1 [6:0] 0 0080h r1682 (692h) out2lmix input 2 source out2l mix_s ts2 0 0 0 0 0 0 0 out2lmix_src2 [7:0] 0000h r1683 (693h) out2lmix input 2 volume 0 0 0 0 0 0 0 0 out2lmix_vol2 [6:0] 0 0080h r1684 (694h) out2lmix input 3 source out2l mix_s ts3 0 0 0 0 0 0 0 out2lmix_src3 [7:0] 0000h r1685 (695h) out2lmix input 3 volume 0 0 0 0 0 0 0 0 out2lmix_vol3 [6:0] 0 0080h r1686 (696h) out2lmix input 4 source out2l mix_s ts4 0 0 0 0 0 0 0 out2lmix_src4 [7:0] 0000h r1687 (697h) out2lmix input 4 volume 0 0 0 0 0 0 0 0 out2lmix_vol4 [6:0] 0 0080h r1688 (698h) out2rmix input 1 source out2 rmix_ sts1 0 0 0 0 0 0 0 out2rmix_src1 [7:0] 0000h r1689 (699h) out2rmix input 1 volume 0 0 0 0 0 0 0 0 out2rmix_vol1 [6:0] 0 0080h r1690 (69ah) out2rmix input 2 source out2 rmix_ sts2 0 0 0 0 0 0 0 out2rmix_src2 [7:0] 0000h r1691 (69bh) out2rmix input 2 volume 0 0 0 0 0 0 0 0 out2rmix_vol2 [6:0] 0 0080h r1692 (69ch) out2rmix input 3 source out2 rmix_ sts3 0 0 0 0 0 0 0 out2rmix_src3 [7:0] 0000h r1693 (69dh) out2rmix input 3 volume 0 0 0 0 0 0 0 0 out2rmix_vol3 [6:0] 0 0080h r1694 (69eh) out2rmix input 4 source out2 rmix_ sts4 0 0 0 0 0 0 0 out2rmix_src4 [7:0] 0000h r1695 (69fh) out2rmix input 4 volume 0 0 0 0 0 0 0 0 out2rmix_vol4 [6:0] 0 0080h r1696 (6a0h) out3lmix input 1 source out3 mix_s ts1 0 0 0 0 0 0 0 out3mix_src1 [7:0] 0000h r1697 (6a1h) out3lmix input 1 volume 0 0 0 0 0 0 0 0 out3mix_vol1 [6:0] 0 0080h r1698 (6a2h) out3lmix input 2 source out3 mix_s ts2 0 0 0 0 0 0 0 out3mix_src2 [7:0] 0000h r1699 (6a3h) out3lmix input 2 volume 0 0 0 0 0 0 0 0 out3mix_vol2 [6:0] 0 0080h
production data WM5102 w pd, may 2013, rev 4.0 273 reg name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 default r1700 (6a4h) out3lmix input 3 source out3 mix_s ts3 0 0 0 0 0 0 0 out3mix_src3 [7:0] 0000h r1701 (6a5h) out3lmix input 3 volume 0 0 0 0 0 0 0 0 out3mix_vol3 [6:0] 0 0080h r1702 (6a6h) out3lmix input 4 source out3 mix_s ts4 0 0 0 0 0 0 0 out3mix_src4 [7:0] 0000h r1703 (6a7h) out3lmix input 4 volume 0 0 0 0 0 0 0 0 out3mix_vol4 [6:0] 0 0080h r1712 (6b0h) out4lmix input 1 source out4l mix_s ts1 0 0 0 0 0 0 0 out4lmix_src1 [7:0] 0000h r1713 (6b1h) out4lmix input 1 volume 0 0 0 0 0 0 0 0 out4lmix_vol1 [6:0] 0 0080h r1714 (6b2h) out4lmix input 2 source out4l mix_s ts2 0 0 0 0 0 0 0 out4lmix_src2 [7:0] 0000h r1715 (6b3h) out4lmix input 2 volume 0 0 0 0 0 0 0 0 out4lmix_vol2 [6:0] 0 0080h r1716 (6b4h) out4lmix input 3 source out4l mix_s ts3 0 0 0 0 0 0 0 out4lmix_src3 [7:0] 0000h r1717 (6b5h) out4lmix input 3 volume 0 0 0 0 0 0 0 0 out4lmix_vol3 [6:0] 0 0080h r1718 (6b6h) out4lmix input 4 source out4l mix_s ts4 0 0 0 0 0 0 0 out4lmix_src4 [7:0] 0000h r1719 (6b7h) out4lmix input 4 volume 0 0 0 0 0 0 0 0 out4lmix_vol4 [6:0] 0 0080h r1720 (6b8h) out4rmix input 1 source out4 rmix_ sts1 0 0 0 0 0 0 0 out4rmix_src1 [7:0] 0000h r1721 (6b9h) out4rmix input 1 volume 0 0 0 0 0 0 0 0 out4rmix_vol1 [6:0] 0 0080h r1722 (6bah) out4rmix input 2 source out4 rmix_ sts2 0 0 0 0 0 0 0 out4rmix_src2 [7:0] 0000h r1723 (6bbh) out4rmix input 2 volume 0 0 0 0 0 0 0 0 out4rmix_vol2 [6:0] 0 0080h r1724 (6bch) out4rmix input 3 source out4 rmix_ sts3 0 0 0 0 0 0 0 out4rmix_src3 [7:0] 0000h r1725 (6bdh) out4rmix input 3 volume 0 0 0 0 0 0 0 0 out4rmix_vol3 [6:0] 0 0080h r1726 (6beh) out4rmix input 4 source out4 rmix_ sts4 0 0 0 0 0 0 0 out4rmix_src4 [7:0] 0000h r1727 (6bfh) out4rmix input 4 volume 0 0 0 0 0 0 0 0 out4rmix_vol4 [6:0] 0 0080h r1728 (6c0h) out5lmix input 1 source out5l mix_s ts1 0 0 0 0 0 0 0 out5lmix_src1 [7:0] 0000h r1729 (6c1h) out5lmix input 1 volume 0 0 0 0 0 0 0 0 out5lmix_vol1 [6:0] 0 0080h r1730 (6c2h) out5lmix input 2 source out5l mix_s ts2 0 0 0 0 0 0 0 out5lmix_src2 [7:0] 0000h
WM5102 production data w pd, may 2013, rev 4.0 274 reg name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 default r1731 (6c3h) out5lmix input 2 volume 0 0 0 0 0 0 0 0 out5lmix_vol2 [6:0] 0 0080h r1732 (6c4h) out5lmix input 3 source out5l mix_s ts3 0 0 0 0 0 0 0 out5lmix_src3 [7:0] 0000h r1733 (6c5h) out5lmix input 3 volume 0 0 0 0 0 0 0 0 out5lmix_vol3 [6:0] 0 0080h r1734 (6c6h) out5lmix input 4 source out5l mix_s ts4 0 0 0 0 0 0 0 out5lmix_src4 [7:0] 0000h r1735 (6c7h) out5lmix input 4 volume 0 0 0 0 0 0 0 0 out5lmix_vol4 [6:0] 0 0080h r1736 (6c8h) out5rmix input 1 source out5 rmix_ sts1 0 0 0 0 0 0 0 out5rmix_src1 [7:0] 0000h r1737 (6c9h) out5rmix input 1 volume 0 0 0 0 0 0 0 0 out5rmix_vol1 [6:0] 0 0080h r1738 (6cah) out5rmix input 2 source out5 rmix_ sts2 0 0 0 0 0 0 0 out5rmix_src2 [7:0] 0000h r1739 (6cbh) out5rmix input 2 volume 0 0 0 0 0 0 0 0 out5rmix_vol2 [6:0] 0 0080h r1740 (6cch) out5rmix input 3 source out5 rmix_ sts3 0 0 0 0 0 0 0 out5rmix_src3 [7:0] 0000h r1741 (6cdh) out5rmix input 3 volume 0 0 0 0 0 0 0 0 out5rmix_vol3 [6:0] 0 0080h r1742 (6ceh) out5rmix input 4 source out5 rmix_ sts4 0 0 0 0 0 0 0 out5rmix_src4 [7:0] 0000h r1743 (6cfh) out5rmix input 4 volume 0 0 0 0 0 0 0 0 out5rmix_vol4 [6:0] 0 0080h r1792 (700h) aif1tx1mix input 1 source aif1t x1mix _sts1 0 0 0 0 0 0 0 aif1tx1mix_src1 [7:0] 0000h r1793 (701h) aif1tx1mix input 1 volume 0 0 0 0 0 0 0 0 aif1tx1mix_vol1 [6:0] 0 0080h r1794 (702h) aif1tx1mix input 2 source aif1t x1mix _sts2 0 0 0 0 0 0 0 aif1tx1mix_src2 [7:0] 0000h r1795 (703h) aif1tx1mix input 2 volume 0 0 0 0 0 0 0 0 aif1tx1mix_vol2 [6:0] 0 0080h r1796 (704h) aif1tx1mix input 3 source aif1t x1mix _sts3 0 0 0 0 0 0 0 aif1tx1mix_src3 [7:0] 0000h r1797 (705h) aif1tx1mix input 3 volume 0 0 0 0 0 0 0 0 aif1tx1mix_vol3 [6:0] 0 0080h r1798 (706h) aif1tx1mix input 4 source aif1t x1mix _sts4 0 0 0 0 0 0 0 aif1tx1mix_src4 [7:0] 0000h r1799 (707h) aif1tx1mix input 4 volume 0 0 0 0 0 0 0 0 aif1tx1mix_vol4 [6:0] 0 0080h r1800 (708h) aif1tx2mix input 1 source aif1t x2mix _sts1 0 0 0 0 0 0 0 aif1tx2mix_src1 [7:0] 0000h r1801 (709h) aif1tx2mix input 1 volume 0 0 0 0 0 0 0 0 aif1tx2mix_vol1 [6:0] 0 0080h
production data WM5102 w pd, may 2013, rev 4.0 275 reg name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 default r1802 (70ah) aif1tx2mix input 2 source aif1t x2mix _sts2 0 0 0 0 0 0 0 aif1tx2mix_src2 [7:0] 0000h r1803 (70bh) aif1tx2mix input 2 volume 0 0 0 0 0 0 0 0 aif1tx2mix_vol2 [6:0] 0 0080h r1804 (70ch) aif1tx2mix input 3 source aif1t x2mix _sts3 0 0 0 0 0 0 0 aif1tx2mix_src3 [7:0] 0000h r1805 (70dh) aif1tx2mix input 3 volume 0 0 0 0 0 0 0 0 aif1tx2mix_vol3 [6:0] 0 0080h r1806 (70eh) aif1tx2mix input 4 source aif1t x2mix _sts4 0 0 0 0 0 0 0 aif1tx2mix_src4 [7:0] 0000h r1807 (70fh) aif1tx2mix input 4 volume 0 0 0 0 0 0 0 0 aif1tx2mix_vol4 [6:0] 0 0080h r1808 (710h) aif1tx3mix input 1 source aif1t x3mix _sts1 0 0 0 0 0 0 0 aif1tx3mix_src1 [7:0] 0000h r1809 (711h) aif1tx3mix input 1 volume 0 0 0 0 0 0 0 0 aif1tx3mix_vol1 [6:0] 0 0080h r1810 (712h) aif1tx3mix input 2 source aif1t x3mix _sts2 0 0 0 0 0 0 0 aif1tx3mix_src2 [7:0] 0000h r1811 (713h) aif1tx3mix input 2 volume 0 0 0 0 0 0 0 0 aif1tx3mix_vol2 [6:0] 0 0080h r1812 (714h) aif1tx3mix input 3 source aif1t x3mix _sts3 0 0 0 0 0 0 0 aif1tx3mix_src3 [7:0] 0000h r1813 (715h) aif1tx3mix input 3 volume 0 0 0 0 0 0 0 0 aif1tx3mix_vol3 [6:0] 0 0080h r1814 (716h) aif1tx3mix input 4 source aif1t x3mix _sts4 0 0 0 0 0 0 0 aif1tx3mix_src4 [7:0] 0000h r1815 (717h) aif1tx3mix input 4 volume 0 0 0 0 0 0 0 0 aif1tx3mix_vol4 [6:0] 0 0080h r1816 (718h) aif1tx4mix input 1 source aif1t x4mix _sts1 0 0 0 0 0 0 0 aif1tx4mix_src1 [7:0] 0000h r1817 (719h) aif1tx4mix input 1 volume 0 0 0 0 0 0 0 0 aif1tx4mix_vol1 [6:0] 0 0080h r1818 (71ah) aif1tx4mix input 2 source aif1t x4mix _sts2 0 0 0 0 0 0 0 aif1tx4mix_src2 [7:0] 0000h r1819 (71bh) aif1tx4mix input 2 volume 0 0 0 0 0 0 0 0 aif1tx4mix_vol2 [6:0] 0 0080h r1820 (71ch) aif1tx4mix input 3 source aif1t x4mix _sts3 0 0 0 0 0 0 0 aif1tx4mix_src3 [7:0] 0000h r1821 (71dh) aif1tx4mix input 3 volume 0 0 0 0 0 0 0 0 aif1tx4mix_vol3 [6:0] 0 0080h r1822 (71eh) aif1tx4mix input 4 source aif1t x4mix _sts4 0 0 0 0 0 0 0 aif1tx4mix_src4 [7:0] 0000h r1823 (71fh) aif1tx4mix input 4 volume 0 0 0 0 0 0 0 0 aif1tx4mix_vol4 [6:0] 0 0080h r1824 (720h) aif1tx5mix input 1 source aif1t x5mix _sts1 0 0 0 0 0 0 0 aif1tx5mix_src1 [7:0] 0000h
WM5102 production data w pd, may 2013, rev 4.0 276 reg name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 default r1825 (721h) aif1tx5mix input 1 volume 0 0 0 0 0 0 0 0 aif1tx5mix_vol1 [6:0] 0 0080h r1826 (722h) aif1tx5mix input 2 source aif1t x5mix _sts2 0 0 0 0 0 0 0 aif1tx5mix_src2 [7:0] 0000h r1827 (723h) aif1tx5mix input 2 volume 0 0 0 0 0 0 0 0 aif1tx5mix_vol2 [6:0] 0 0080h r1828 (724h) aif1tx5mix input 3 source aif1t x5mix _sts3 0 0 0 0 0 0 0 aif1tx5mix_src3 [7:0] 0000h r1829 (725h) aif1tx5mix input 3 volume 0 0 0 0 0 0 0 0 aif1tx5mix_vol3 [6:0] 0 0080h r1830 (726h) aif1tx5mix input 4 source aif1t x5mix _sts4 0 0 0 0 0 0 0 aif1tx5mix_src4 [7:0] 0000h r1831 (727h) aif1tx5mix input 4 volume 0 0 0 0 0 0 0 0 aif1tx5mix_vol4 [6:0] 0 0080h r1832 (728h) aif1tx6mix input 1 source aif1t x6mix _sts1 0 0 0 0 0 0 0 aif1tx6mix_src1 [7:0] 0000h r1833 (729h) aif1tx6mix input 1 volume 0 0 0 0 0 0 0 0 aif1tx6mix_vol1 [6:0] 0 0080h r1834 (72ah) aif1tx6mix input 2 source aif1t x6mix _sts2 0 0 0 0 0 0 0 aif1tx6mix_src2 [7:0] 0000h r1835 (72bh) aif1tx6mix input 2 volume 0 0 0 0 0 0 0 0 aif1tx6mix_vol2 [6:0] 0 0080h r1836 (72ch) aif1tx6mix input 3 source aif1t x6mix _sts3 0 0 0 0 0 0 0 aif1tx6mix_src3 [7:0] 0000h r1837 (72dh) aif1tx6mix input 3 volume 0 0 0 0 0 0 0 0 aif1tx6mix_vol3 [6:0] 0 0080h r1838 (72eh) aif1tx6mix input 4 source aif1t x6mix _sts4 0 0 0 0 0 0 0 aif1tx6mix_src4 [7:0] 0000h r1839 (72fh) aif1tx6mix input 4 volume 0 0 0 0 0 0 0 0 aif1tx6mix_vol4 [6:0] 0 0080h r1840 (730h) aif1tx7mix input 1 source aif1t x7mix _sts1 0 0 0 0 0 0 0 aif1tx7mix_src1 [7:0] 0000h r1841 (731h) aif1tx7mix input 1 volume 0 0 0 0 0 0 0 0 aif1tx7mix_vol1 [6:0] 0 0080h r1842 (732h) aif1tx7mix input 2 source aif1t x7mix _sts2 0 0 0 0 0 0 0 aif1tx7mix_src2 [7:0] 0000h r1843 (733h) aif1tx7mix input 2 volume 0 0 0 0 0 0 0 0 aif1tx7mix_vol2 [6:0] 0 0080h r1844 (734h) aif1tx7mix input 3 source aif1t x7mix _sts3 0 0 0 0 0 0 0 aif1tx7mix_src3 [7:0] 0000h r1845 (735h) aif1tx7mix input 3 volume 0 0 0 0 0 0 0 0 aif1tx7mix_vol3 [6:0] 0 0080h r1846 (736h) aif1tx7mix input 4 source aif1t x7mix _sts4 0 0 0 0 0 0 0 aif1tx7mix_src4 [7:0] 0000h r1847 (737h) aif1tx7mix input 4 volume 0 0 0 0 0 0 0 0 aif1tx7mix_vol4 [6:0] 0 0080h
production data WM5102 w pd, may 2013, rev 4.0 277 reg name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 default r1848 (738h) aif1tx8mix input 1 source aif1t x8mix _sts1 0 0 0 0 0 0 0 aif1tx8mix_src1 [7:0] 0000h r1849 (739h) aif1tx8mix input 1 volume 0 0 0 0 0 0 0 0 aif1tx8mix_vol1 [6:0] 0 0080h r1850 (73ah) aif1tx8mix input 2 source aif1t x8mix _sts2 0 0 0 0 0 0 0 aif1tx8mix_src2 [7:0] 0000h r1851 (73bh) aif1tx8mix input 2 volume 0 0 0 0 0 0 0 0 aif1tx8mix_vol2 [6:0] 0 0080h r1852 (73ch) aif1tx8mix input 3 source aif1t x8mix _sts3 0 0 0 0 0 0 0 aif1tx8mix_src3 [7:0] 0000h r1853 (73dh) aif1tx8mix input 3 volume 0 0 0 0 0 0 0 0 aif1tx8mix_vol3 [6:0] 0 0080h r1854 (73eh) aif1tx8mix input 4 source aif1t x8mix _sts4 0 0 0 0 0 0 0 aif1tx8mix_src4 [7:0] 0000h r1855 (73fh) aif1tx8mix input 4 volume 0 0 0 0 0 0 0 0 aif1tx8mix_vol4 [6:0] 0 0080h r1856 (740h) aif2tx1mix input 1 source aif2t x1mix _sts1 0 0 0 0 0 0 0 aif2tx1mix_src1 [7:0] 0000h r1857 (741h) aif2tx1mix input 1 volume 0 0 0 0 0 0 0 0 aif2tx1mix_vol1 [6:0] 0 0080h r1858 (742h) aif2tx1mix input 2 source aif2t x1mix _sts2 0 0 0 0 0 0 0 aif2tx1mix_src2 [7:0] 0000h r1859 (743h) aif2tx1mix input 2 volume 0 0 0 0 0 0 0 0 aif2tx1mix_vol2 [6:0] 0 0080h r1860 (744h) aif2tx1mix input 3 source aif2t x1mix _sts3 0 0 0 0 0 0 0 aif2tx1mix_src3 [7:0] 0000h r1861 (745h) aif2tx1mix input 3 volume 0 0 0 0 0 0 0 0 aif2tx1mix_vol3 [6:0] 0 0080h r1862 (746h) aif2tx1mix input 4 source aif2t x1mix _sts4 0 0 0 0 0 0 0 aif2tx1mix_src4 [7:0] 0000h r1863 (747h) aif2tx1mix input 4 volume 0 0 0 0 0 0 0 0 aif2tx1mix_vol4 [6:0] 0 0080h r1864 (748h) aif2tx2mix input 1 source aif2t x2mix _sts1 0 0 0 0 0 0 0 aif2tx2mix_src1 [7:0] 0000h r1865 (749h) aif2tx2mix input 1 volume 0 0 0 0 0 0 0 0 aif2tx2mix_vol1 [6:0] 0 0080h r1866 (74ah) aif2tx2mix input 2 source aif2t x2mix _sts2 0 0 0 0 0 0 0 aif2tx2mix_src2 [7:0] 0000h r1867 (74bh) aif2tx2mix input 2 volume 0 0 0 0 0 0 0 0 aif2tx2mix_vol2 [6:0] 0 0080h r1868 (74ch) aif2tx2mix input 3 source aif2t x2mix _sts3 0 0 0 0 0 0 0 aif2tx2mix_src3 [7:0] 0000h r1869 (74dh) aif2tx2mix input 3 volume 0 0 0 0 0 0 0 0 aif2tx2mix_vol3 [6:0] 0 0080h r1870 (74eh) aif2tx2mix input 4 source aif2t x2mix _sts4 0 0 0 0 0 0 0 aif2tx2mix_src4 [7:0] 0000h
WM5102 production data w pd, may 2013, rev 4.0 278 reg name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 default r1871 (74fh) aif2tx2mix input 4 volume 0 0 0 0 0 0 0 0 aif2tx2mix_vol4 [6:0] 0 0080h r1920 (780h) aif3tx1mix input 1 source aif3t x1mix _sts1 0 0 0 0 0 0 0 aif3tx1mix_src1 [7:0] 0000h r1921 (781h) aif3tx1mix input 1 volume 0 0 0 0 0 0 0 0 aif3tx1mix_vol1 [6:0] 0 0080h r1922 (782h) aif3tx1mix input 2 source aif3t x1mix _sts2 0 0 0 0 0 0 0 aif3tx1mix_src2 [7:0] 0000h r1923 (783h) aif3tx1mix input 2 volume 0 0 0 0 0 0 0 0 aif3tx1mix_vol2 [6:0] 0 0080h r1924 (784h) aif3tx1mix input 3 source aif3t x1mix _sts3 0 0 0 0 0 0 0 aif3tx1mix_src3 [7:0] 0000h r1925 (785h) aif3tx1mix input 3 volume 0 0 0 0 0 0 0 0 aif3tx1mix_vol3 [6:0] 0 0080h r1926 (786h) aif3tx1mix input 4 source aif3t x1mix _sts4 0 0 0 0 0 0 0 aif3tx1mix_src4 [7:0] 0000h r1927 (787h) aif3tx1mix input 4 volume 0 0 0 0 0 0 0 0 aif3tx1mix_vol4 [6:0] 0 0080h r1928 (788h) aif3tx2mix input 1 source aif3t x2mix _sts1 0 0 0 0 0 0 0 aif3tx2mix_src1 [7:0] 0000h r1929 (789h) aif3tx2mix input 1 volume 0 0 0 0 0 0 0 0 aif3tx2mix_vol1 [6:0] 0 0080h r1930 (78ah) aif3tx2mix input 2 source aif3t x2mix _sts2 0 0 0 0 0 0 0 aif3tx2mix_src2 [7:0] 0000h r1931 (78bh) aif3tx2mix input 2 volume 0 0 0 0 0 0 0 0 aif3tx2mix_vol2 [6:0] 0 0080h r1932 (78ch) aif3tx2mix input 3 source aif3t x2mix _sts3 0 0 0 0 0 0 0 aif3tx2mix_src3 [7:0] 0000h r1933 (78dh) aif3tx2mix input 3 volume 0 0 0 0 0 0 0 0 aif3tx2mix_vol3 [6:0] 0 0080h r1934 (78eh) aif3tx2mix input 4 source aif3t x2mix _sts4 0 0 0 0 0 0 0 aif3tx2mix_src4 [7:0] 0000h r1935 (78fh) aif3tx2mix input 4 volume 0 0 0 0 0 0 0 0 aif3tx2mix_vol4 [6:0] 0 0080h r1984 (7c0h) slimtx1mix input 1 source slimt x1mix _sts1 0 0 0 0 0 0 0 slimtx1mix_src1 [7:0] 0000h r1985 (7c1h) slimtx1mix input 1 volume 0 0 0 0 0 0 0 0 slimtx1mix_vol1 [6:0] 0 0080h r1986 (7c2h) slimtx1mix input 2 source slimt x1mix _sts2 0 0 0 0 0 0 0 slimtx1mix_src2 [7:0] 0000h r1987 (7c3h) slimtx1mix input 2 volume 0 0 0 0 0 0 0 0 slimtx1mix_vol2 [6:0] 0 0080h r1988 (7c4h) slimtx1mix input 3 source slimt x1mix _sts3 0 0 0 0 0 0 0 slimtx1mix_src3 [7:0] 0000h r1989 (7c5h) slimtx1mix input 3 volume 0 0 0 0 0 0 0 0 slimtx1mix_vol3 [6:0] 0 0080h
production data WM5102 w pd, may 2013, rev 4.0 279 reg name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 default r1990 (7c6h) slimtx1mix input 4 source slimt x1mix _sts4 0 0 0 0 0 0 0 slimtx1mix_src4 [7:0] 0000h r1991 (7c7h) slimtx1mix input 4 volume 0 0 0 0 0 0 0 0 slimtx1mix_vol4 [6:0] 0 0080h r1992 (7c8h) slimtx2mix input 1 source slimt x2mix _sts1 0 0 0 0 0 0 0 slimtx2mix_src1 [7:0] 0000h r1993 (7c9h) slimtx2mix input 1 volume 0 0 0 0 0 0 0 0 slimtx2mix_vol1 [6:0] 0 0080h r1994 (7cah) slimtx2mix input 2 source slimt x2mix _sts2 0 0 0 0 0 0 0 slimtx2mix_src2 [7:0] 0000h r1995 (7cbh) slimtx2mix input 2 volume 0 0 0 0 0 0 0 0 slimtx2mix_vol2 [6:0] 0 0080h r1996 (7cch) slimtx2mix input 3 source slimt x2mix _sts3 0 0 0 0 0 0 0 slimtx2mix_src3 [7:0] 0000h r1997 (7cdh) slimtx2mix input 3 volume 0 0 0 0 0 0 0 0 slimtx2mix_vol3 [6:0] 0 0080h r1998 (7ceh) slimtx2mix input 4 source slimt x2mix _sts4 0 0 0 0 0 0 0 slimtx2mix_src4 [7:0] 0000h r1999 (7cfh) slimtx2mix input 4 volume 0 0 0 0 0 0 0 0 slimtx2mix_vol4 [6:0] 0 0080h r2000 (7d0h) slimtx3mix input 1 source slimt x3mix _sts1 0 0 0 0 0 0 0 slimtx3mix_src1 [7:0] 0000h r2001 (7d1h) slimtx3mix input 1 volume 0 0 0 0 0 0 0 0 slimtx3mix_vol1 [6:0] 0 0080h r2002 (7d2h) slimtx3mix input 2 source slimt x3mix _sts2 0 0 0 0 0 0 0 slimtx3mix_src2 [7:0] 0000h r2003 (7d3h) slimtx3mix input 2 volume 0 0 0 0 0 0 0 0 slimtx3mix_vol2 [6:0] 0 0080h r2004 (7d4h) slimtx3mix input 3 source slimt x3mix _sts3 0 0 0 0 0 0 0 slimtx3mix_src3 [7:0] 0000h r2005 (7d5h) slimtx3mix input 3 volume 0 0 0 0 0 0 0 0 slimtx3mix_vol3 [6:0] 0 0080h r2006 (7d6h) slimtx3mix input 4 source slimt x3mix _sts4 0 0 0 0 0 0 0 slimtx3mix_src4 [7:0] 0000h r2007 (7d7h) slimtx3mix input 4 volume 0 0 0 0 0 0 0 0 slimtx3mix_vol4 [6:0] 0 0080h r2008 (7d8h) slimtx4mix input 1 source slimt x4mix _sts1 0 0 0 0 0 0 0 slimtx4mix_src1 [7:0] 0000h r2009 (7d9h) slimtx4mix input 1 volume 0 0 0 0 0 0 0 0 slimtx4mix_vol1 [6:0] 0 0080h r2010 (7dah) slimtx4mix input 2 source slimt x4mix _sts2 0 0 0 0 0 0 0 slimtx4mix_src2 [7:0] 0000h r2011 (7dbh) slimtx4mix input 2 volume 0 0 0 0 0 0 0 0 slimtx4mix_vol2 [6:0] 0 0080h r2012 (7dch) slimtx4mix input 3 source slimt x4mix _sts3 0 0 0 0 0 0 0 slimtx4mix_src3 [7:0] 0000h
WM5102 production data w pd, may 2013, rev 4.0 280 reg name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 default r2013 (7ddh) slimtx4mix input 3 volume 0 0 0 0 0 0 0 0 slimtx4mix_vol3 [6:0] 0 0080h r2014 (7deh) slimtx4mix input 4 source slimt x4mix _sts4 0 0 0 0 0 0 0 slimtx4mix_src4 [7:0] 0000h r2015 (7dfh) slimtx4mix input 4 volume 0 0 0 0 0 0 0 0 slimtx4mix_vol4 [6:0] 0 0080h r2016 (7e0h) slimtx5mix input 1 source slimt x5mix _sts1 0 0 0 0 0 0 0 slimtx5mix_src1 [7:0] 0000h r2017 (7e1h) slimtx5mix input 1 volume 0 0 0 0 0 0 0 0 slimtx5mix_vol1 [6:0] 0 0080h r2018 (7e2h) slimtx5mix input 2 source slimt x5mix _sts2 0 0 0 0 0 0 0 slimtx5mix_src2 [7:0] 0000h r2019 (7e3h) slimtx5mix input 2 volume 0 0 0 0 0 0 0 0 slimtx5mix_vol2 [6:0] 0 0080h r2020 (7e4h) slimtx5mix input 3 source slimt x5mix _sts3 0 0 0 0 0 0 0 slimtx5mix_src3 [7:0] 0000h r2021 (7e5h) slimtx5mix input 3 volume 0 0 0 0 0 0 0 0 slimtx5mix_vol3 [6:0] 0 0080h r2022 (7e6h) slimtx5mix input 4 source slimt x5mix _sts4 0 0 0 0 0 0 0 slimtx5mix_src4 [7:0] 0000h r2023 (7e7h) slimtx5mix input 4 volume 0 0 0 0 0 0 0 0 slimtx5mix_vol4 [6:0] 0 0080h r2024 (7e8h) slimtx6mix input 1 source slimt x6mix _sts1 0 0 0 0 0 0 0 slimtx6mix_src1 [7:0] 0000h r2025 (7e9h) slimtx6mix input 1 volume 0 0 0 0 0 0 0 0 slimtx6mix_vol1 [6:0] 0 0080h r2026 (7eah) slimtx6mix input 2 source slimt x6mix _sts2 0 0 0 0 0 0 0 slimtx6mix_src2 [7:0] 0000h r2027 (7ebh) slimtx6mix input 2 volume 0 0 0 0 0 0 0 0 slimtx6mix_vol2 [6:0] 0 0080h r2028 (7ech) slimtx6mix input 3 source slimt x6mix _sts3 0 0 0 0 0 0 0 slimtx6mix_src3 [7:0] 0000h r2029 (7edh) slimtx6mix input 3 volume 0 0 0 0 0 0 0 0 slimtx6mix_vol3 [6:0] 0 0080h r2030 (7eeh) slimtx6mix input 4 source slimt x6mix _sts4 0 0 0 0 0 0 0 slimtx6mix_src4 [7:0] 0000h r2031 (7efh) slimtx6mix input 4 volume 0 0 0 0 0 0 0 0 slimtx6mix_vol4 [6:0] 0 0080h r2032 (7f0h) slimtx7mix input 1 source slimt x7mix _sts1 0 0 0 0 0 0 0 slimtx7mix_src1 [7:0] 0000h r2033 (7f1h) slimtx7mix input 1 volume 0 0 0 0 0 0 0 0 slimtx7mix_vol1 [6:0] 0 0080h r2034 (7f2h) slimtx7mix input 2 source slimt x7mix _sts2 0 0 0 0 0 0 0 slimtx7mix_src2 [7:0] 0000h r2035 (7f3h) slimtx7mix input 2 volume 0 0 0 0 0 0 0 0 slimtx7mix_vol2 [6:0] 0 0080h
production data WM5102 w pd, may 2013, rev 4.0 281 reg name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 default r2036 (7f4h) slimtx7mix input 3 source slimt x7mix _sts3 0 0 0 0 0 0 0 slimtx7mix_src3 [7:0] 0000h r2037 (7f5h) slimtx7mix input 3 volume 0 0 0 0 0 0 0 0 slimtx7mix_vol3 [6:0] 0 0080h r2038 (7f6h) slimtx7mix input 4 source slimt x7mix _sts4 0 0 0 0 0 0 0 slimtx7mix_src4 [7:0] 0000h r2039 (7f7h) slimtx7mix input 4 volume 0 0 0 0 0 0 0 0 slimtx7mix_vol4 [6:0] 0 0080h r2040 (7f8h) slimtx8mix input 1 source slimt x8mix _sts1 0 0 0 0 0 0 0 slimtx8mix_src1 [7:0] 0000h r2041 (7f9h) slimtx8mix input 1 volume 0 0 0 0 0 0 0 0 slimtx8mix_vol1 [6:0] 0 0080h r2042 (7fah) slimtx8mix input 2 source slimt x8mix _sts2 0 0 0 0 0 0 0 slimtx8mix_src2 [7:0] 0000h r2043 (7fbh) slimtx8mix input 2 volume 0 0 0 0 0 0 0 0 slimtx8mix_vol2 [6:0] 0 0080h r2044 (7fch) slimtx8mix input 3 source slimt x8mix _sts3 0 0 0 0 0 0 0 slimtx8mix_src3 [7:0] 0000h r2045 (7fdh) slimtx8mix input 3 volume 0 0 0 0 0 0 0 0 slimtx8mix_vol3 [6:0] 0 0080h r2046 (7feh) slimtx8mix input 4 source slimt x8mix _sts4 0 0 0 0 0 0 0 slimtx8mix_src4 [7:0] 0000h r2047 (7ffh) slimtx8mix input 4 volume 0 0 0 0 0 0 0 0 slimtx8mix_vol4 [6:0] 0 0080h r2176 (880h) eq1mix input 1 source eq1mi x_sts 1 0 0 0 0 0 0 0 eq1mix_src1 [7:0] 0000h r2177 (881h) eq1mix input 1 volume 0 0 0 0 0 0 0 0 eq1mix_vol1 [6:0] 0 0080h r2178 (882h) eq1mix input 2 source eq1mi x_sts 2 0 0 0 0 0 0 0 eq1mix_src2 [7:0] 0000h r2179 (883h) eq1mix input 2 volume 0 0 0 0 0 0 0 0 eq1mix_vol2 [6:0] 0 0080h r2180 (884h) eq1mix input 3 source eq1mi x_sts 3 0 0 0 0 0 0 0 eq1mix_src3 [7:0] 0000h r2181 (885h) eq1mix input 3 volume 0 0 0 0 0 0 0 0 eq1mix_vol3 [6:0] 0 0080h r2182 (886h) eq1mix input 4 source eq1mi x_sts 4 0 0 0 0 0 0 0 eq1mix_src4 [7:0] 0000h r2183 (887h) eq1mix input 4 volume 0 0 0 0 0 0 0 0 eq1mix_vol4 [6:0] 0 0080h r2184 (888h) eq2mix input 1 source eq2mi x_sts 1 0 0 0 0 0 0 0 eq2mix_src1 [7:0] 0000h r2185 (889h) eq2mix input 1 volume 0 0 0 0 0 0 0 0 eq2mix_vol1 [6:0] 0 0080h r2186 (88ah) eq2mix input 2 source eq2mi x_sts 2 0 0 0 0 0 0 0 eq2mix_src2 [7:0] 0000h
WM5102 production data w pd, may 2013, rev 4.0 282 reg name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 default r2187 (88bh) eq2mix input 2 volume 0 0 0 0 0 0 0 0 eq2mix_vol2 [6:0] 0 0080h r2188 (88ch) eq2mix input 3 source eq2mi x_sts 3 0 0 0 0 0 0 0 eq2mix_src3 [7:0] 0000h r2189 (88dh) eq2mix input 3 volume 0 0 0 0 0 0 0 0 eq2mix_vol3 [6:0] 0 0080h r2190 (88eh) eq2mix input 4 source eq2mi x_sts 4 0 0 0 0 0 0 0 eq2mix_src4 [7:0] 0000h r2191 (88fh) eq2mix input 4 volume 0 0 0 0 0 0 0 0 eq2mix_vol4 [6:0] 0 0080h r2192 (890h) eq3mix input 1 source eq3mi x_sts 1 0 0 0 0 0 0 0 eq3mix_src1 [7:0] 0000h r2193 (891h) eq3mix input 1 volume 0 0 0 0 0 0 0 0 eq3mix_vol1 [6:0] 0 0080h r2194 (892h) eq3mix input 2 source eq3mi x_sts 2 0 0 0 0 0 0 0 eq3mix_src2 [7:0] 0000h r2195 (893h) eq3mix input 2 volume 0 0 0 0 0 0 0 0 eq3mix_vol2 [6:0] 0 0080h r2196 (894h) eq3mix input 3 source eq3mi x_sts 3 0 0 0 0 0 0 0 eq3mix_src3 [7:0] 0000h r2197 (895h) eq3mix input 3 volume 0 0 0 0 0 0 0 0 eq3mix_vol3 [6:0] 0 0080h r2198 (896h) eq3mix input 4 source eq3mi x_sts 4 0 0 0 0 0 0 0 eq3mix_src4 [7:0] 0000h r2199 (897h) eq3mix input 4 volume 0 0 0 0 0 0 0 0 eq3mix_vol4 [6:0] 0 0080h r2200 (898h) eq4mix input 1 source eq4mi x_sts 1 0 0 0 0 0 0 0 eq4mix_src1 [7:0] 0000h r2201 (899h) eq4mix input 1 volume 0 0 0 0 0 0 0 0 eq4mix_vol1 [6:0] 0 0080h r2202 (89ah) eq4mix input 2 source eq4mi x_sts 2 0 0 0 0 0 0 0 eq4mix_src2 [7:0] 0000h r2203 (89bh) eq4mix input 2 volume 0 0 0 0 0 0 0 0 eq4mix_vol2 [6:0] 0 0080h r2204 (89ch) eq4mix input 3 source eq4mi x_sts 3 0 0 0 0 0 0 0 eq4mix_src3 [7:0] 0000h r2205 (89dh) eq4mix input 3 volume 0 0 0 0 0 0 0 0 eq4mix_vol3 [6:0] 0 0080h r2206 (89eh) eq4mix input 4 source eq4mi x_sts 4 0 0 0 0 0 0 0 eq4mix_src4 [7:0] 0000h r2207 (89fh) eq4mix input 4 volume 0 0 0 0 0 0 0 0 eq4mix_vol4 [6:0] 0 0080h r2240 (8c0h) drc1lmix input 1 source drc1 lmix_ sts1 0 0 0 0 0 0 0 drc1lmix_src1 [7:0] 0000h r2241 (8c1h) drc1lmix input 1 volume 0 0 0 0 0 0 0 0 drc1lmix_vol1 [6:0] 0 0080h
production data WM5102 w pd, may 2013, rev 4.0 283 reg name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 default r2242 (8c2h) drc1lmix input 2 source drc1 lmix_ sts2 0 0 0 0 0 0 0 drc1lmix_src2 [7:0] 0000h r2243 (8c3h) drc1lmix input 2 volume 0 0 0 0 0 0 0 0 drc1lmix_vol2 [6:0] 0 0080h r2244 (8c4h) drc1lmix input 3 source drc1 lmix_ sts3 0 0 0 0 0 0 0 drc1lmix_src3 [7:0] 0000h r2245 (8c5h) drc1lmix input 3 volume 0 0 0 0 0 0 0 0 drc1lmix_vol3 [6:0] 0 0080h r2246 (8c6h) drc1lmix input 4 source drc1 lmix_ sts4 0 0 0 0 0 0 0 drc1lmix_src4 [7:0] 0000h r2247 (8c7h) drc1lmix input 4 volume 0 0 0 0 0 0 0 0 drc1lmix_vol4 [6:0] 0 0080h r2248 (8c8h) drc1rmix input 1 source drc1 rmix_ sts1 0 0 0 0 0 0 0 drc1rmix_src1 [7:0] 0000h r2249 (8c9h) drc1rmix input 1 volume 0 0 0 0 0 0 0 0 drc1rmix_vol1 [6:0] 0 0080h r2250 (8cah) drc1rmix input 2 source drc1 rmix_ sts2 0 0 0 0 0 0 0 drc1rmix_src2 [7:0] 0000h r2251 (8cbh) drc1rmix input 2 volume 0 0 0 0 0 0 0 0 drc1rmix_vol2 [6:0] 0 0080h r2252 (8cch) drc1rmix input 3 source drc1 rmix_ sts3 0 0 0 0 0 0 0 drc1rmix_src3 [7:0] 0000h r2253 (8cdh) drc1rmix input 3 volume 0 0 0 0 0 0 0 0 drc1rmix_vol3 [6:0] 0 0080h r2254 (8ceh) drc1rmix input 4 source drc1 rmix_ sts4 0 0 0 0 0 0 0 drc1rmix_src4 [7:0] 0000h r2255 (8cfh) drc1rmix input 4 volume 0 0 0 0 0 0 0 0 drc1rmix_vol4 [6:0] 0 0080h r2304 (900h) hplp1mix input 1 source lhpf1 mix_s ts1 0 0 0 0 0 0 0 lhpf1mix_src1 [7:0] 0000h r2305 (901h) hplp1mix input 1 volume 0 0 0 0 0 0 0 0 lhpf1mix_vol1 [6:0] 0 0080h r2306 (902h) hplp1mix input 2 source lhpf1 mix_s ts2 0 0 0 0 0 0 0 lhpf1mix_src2 [7:0] 0000h r2307 (903h) hplp1mix input 2 volume 0 0 0 0 0 0 0 0 lhpf1mix_vol2 [6:0] 0 0080h r2308 (904h) hplp1mix input 3 source lhpf1 mix_s ts3 0 0 0 0 0 0 0 lhpf1mix_src3 [7:0] 0000h r2309 (905h) hplp1mix input 3 volume 0 0 0 0 0 0 0 0 lhpf1mix_vol3 [6:0] 0 0080h r2310 (906h) hplp1mix input 4 source lhpf1 mix_s ts4 0 0 0 0 0 0 0 lhpf1mix_src4 [7:0] 0000h r2311 (907h) hplp1mix input 4 volume 0 0 0 0 0 0 0 0 lhpf1mix_vol4 [6:0] 0 0080h r2312 (908h) hplp2mix input 1 source lhpf2 mix_s ts1 0 0 0 0 0 0 0 lhpf2mix_src1 [7:0] 0000h
WM5102 production data w pd, may 2013, rev 4.0 284 reg name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 default r2313 (909h) hplp2mix input 1 volume 0 0 0 0 0 0 0 0 lhpf2mix_vol1 [6:0] 0 0080h r2314 (90ah) hplp2mix input 2 source lhpf2 mix_s ts2 0 0 0 0 0 0 0 lhpf2mix_src2 [7:0] 0000h r2315 (90bh) hplp2mix input 2 volume 0 0 0 0 0 0 0 0 lhpf2mix_vol2 [6:0] 0 0080h r2316 (90ch) hplp2mix input 3 source lhpf2 mix_s ts3 0 0 0 0 0 0 0 lhpf2mix_src3 [7:0] 0000h r2317 (90dh) hplp2mix input 3 volume 0 0 0 0 0 0 0 0 lhpf2mix_vol3 [6:0] 0 0080h r2318 (90eh) hplp2mix input 4 source lhpf2 mix_s ts4 0 0 0 0 0 0 0 lhpf2mix_src4 [7:0] 0000h r2319 (90fh) hplp2mix input 4 volume 0 0 0 0 0 0 0 0 lhpf2mix_vol4 [6:0] 0 0080h r2320 (910h) hplp3mix input 1 source lhpf3 mix_s ts1 0 0 0 0 0 0 0 lhpf3mix_src1 [7:0] 0000h r2321 (911h) hplp3mix input 1 volume 0 0 0 0 0 0 0 0 lhpf3mix_vol1 [6:0] 0 0080h r2322 (912h) hplp3mix input 2 source lhpf3 mix_s ts2 0 0 0 0 0 0 0 lhpf3mix_src2 [7:0] 0000h r2323 (913h) hplp3mix input 2 volume 0 0 0 0 0 0 0 0 lhpf3mix_vol2 [6:0] 0 0080h r2324 (914h) hplp3mix input 3 source lhpf3 mix_s ts3 0 0 0 0 0 0 0 lhpf3mix_src3 [7:0] 0000h r2325 (915h) hplp3mix input 3 volume 0 0 0 0 0 0 0 0 lhpf3mix_vol3 [6:0] 0 0080h r2326 (916h) hplp3mix input 4 source lhpf3 mix_s ts4 0 0 0 0 0 0 0 lhpf3mix_src4 [7:0] 0000h r2327 (917h) hplp3mix input 4 volume 0 0 0 0 0 0 0 0 lhpf3mix_vol4 [6:0] 0 0080h r2328 (918h) hplp4mix input 1 source lhpf4 mix_s ts1 0 0 0 0 0 0 0 lhpf4mix_src1 [7:0] 0000h r2329 (919h) hplp4mix input 1 volume 0 0 0 0 0 0 0 0 lhpf4mix_vol1 [6:0] 0 0080h r2330 (91ah) hplp4mix input 2 source lhpf4 mix_s ts2 0 0 0 0 0 0 0 lhpf4mix_src2 [7:0] 0000h r2331 (91bh) hplp4mix input 2 volume 0 0 0 0 0 0 0 0 lhpf4mix_vol2 [6:0] 0 0080h r2332 (91ch) hplp4mix input 3 source lhpf4 mix_s ts3 0 0 0 0 0 0 0 lhpf4mix_src3 [7:0] 0000h r2333 (91dh) hplp4mix input 3 volume 0 0 0 0 0 0 0 0 lhpf4mix_vol3 [6:0] 0 0080h r2334 (91eh) hplp4mix input 4 source lhpf4 mix_s ts4 0 0 0 0 0 0 0 lhpf4mix_src4 [7:0] 0000h r2335 (91fh) hplp4mix input 4 volume 0 0 0 0 0 0 0 0 lhpf4mix_vol4 [6:0] 0 0080h
production data WM5102 w pd, may 2013, rev 4.0 285 reg name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 default r2368 (940h) dsp1lmix input 1 source dsp1l mix_s ts1 0 0 0 0 0 0 0 dsp1lmix_src1 [7:0] 0000h r2369 (941h) dsp1lmix input 1 volume 0 0 0 0 0 0 0 0 dsp1lmix_vol1 [6:0] 0 0080h r2370 (942h) dsp1lmix input 2 source dsp1l mix_s ts2 0 0 0 0 0 0 0 dsp1lmix_src2 [7:0] 0000h r2371 (943h) dsp1lmix input 2 volume 0 0 0 0 0 0 0 0 dsp1lmix_vol2 [6:0] 0 0080h r2372 (944h) dsp1lmix input 3 source dsp1l mix_s ts3 0 0 0 0 0 0 0 dsp1lmix_src3 [7:0] 0000h r2373 (945h) dsp1lmix input 3 volume 0 0 0 0 0 0 0 0 dsp1lmix_vol3 [6:0] 0 0080h r2374 (946h) dsp1lmix input 4 source dsp1l mix_s ts4 0 0 0 0 0 0 0 dsp1lmix_src4 [7:0] 0000h r2375 (947h) dsp1lmix input 4 volume 0 0 0 0 0 0 0 0 dsp1lmix_vol4 [6:0] 0 0080h r2376 (948h) dsp1rmix input 1 source dsp1 rmix_ sts1 0 0 0 0 0 0 0 dsp1rmix_src1 [7:0] 0000h r2377 (949h) dsp1rmix input 1 volume 0 0 0 0 0 0 0 0 dsp1rmix_vol1 [6:0] 0 0080h r2378 (94ah) dsp1rmix input 2 source dsp1 rmix_ sts2 0 0 0 0 0 0 0 dsp1rmix_src2 [7:0] 0000h r2379 (94bh) dsp1rmix input 2 volume 0 0 0 0 0 0 0 0 dsp1rmix_vol2 [6:0] 0 0080h r2380 (94ch) dsp1rmix input 3 source dsp1 rmix_ sts3 0 0 0 0 0 0 0 dsp1rmix_src3 [7:0] 0000h r2381 (94dh) dsp1rmix input 3 volume 0 0 0 0 0 0 0 0 dsp1rmix_vol3 [6:0] 0 0080h r2382 (94eh) dsp1rmix input 4 source dsp1 rmix_ sts4 0 0 0 0 0 0 0 dsp1rmix_src4 [7:0] 0000h r2383 (94fh) dsp1rmix input 4 volume 0 0 0 0 0 0 0 0 dsp1rmix_vol4 [6:0] 0 0080h r2384 (950h) dsp1aux1mix input 1 source dsp1 aux1 mix_s ts 0 0 0 0 0 0 0 dsp1aux1_src [7:0] 0000h r2392 (958h) dsp1aux2mix input 1 source dsp1 aux2 mix_s ts 0 0 0 0 0 0 0 dsp1aux2_src [7:0] 0000h r2400 (960h) dsp1aux3mix input 1 source dsp1 aux3 mix_s ts 0 0 0 0 0 0 0 dsp1aux3_src [7:0] 0000h r2408 (968h) dsp1aux4mix input 1 source dsp1 aux4 mix_s ts 0 0 0 0 0 0 0 dsp1aux4_src [7:0] 0000h
WM5102 production data w pd, may 2013, rev 4.0 286 reg name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 default r2416 (970h) dsp1aux5mix input 1 source dsp1 aux5 mix_s ts 0 0 0 0 0 0 0 dsp1aux5_src [7:0] 0000h r2424 (978h) dsp1aux6mix input 1 source dsp1 aux6 mix_s ts 0 0 0 0 0 0 0 dsp1aux6_src [7:0] 0000h r2688 (a80h) asrc1lmix input 1 source asrc 1lmix _sts 0 0 0 0 0 0 0 asrc1l_src [7:0] 0000h r2696 (a88h) asrc1rmix input 1 source asrc 1rmix _sts 0 0 0 0 0 0 0 asrc1r_src [7:0] 0000h r2704 (a90h) asrc2lmix input 1 source asrc 2lmix _sts 0 0 0 0 0 0 0 asrc2l_src [7:0] 0000h r2712 (a98h) asrc2rmix input 1 source asrc 2rmix _sts 0 0 0 0 0 0 0 asrc2r_src [7:0] 0000h r2816 (b00h) isrc1dec1mix input 1 source isrc1 dec1 mix_s ts 0 0 0 0 0 0 0 isrc1dec1_src [7:0] 0000h r2824 (b08h) isrc1dec2mix input 1 source isrc1 dec2 mix_s ts 0 0 0 0 0 0 0 isrc1dec2_src [7:0] 0000h r2848 (b20h) isrc1int1mix input 1 source isrc1i nt1mi x_sts 0 0 0 0 0 0 0 isrc1int1_src [7:0] 0000h r2856 (b28h) isrc1int2mix input 1 source isrc1i nt2mi x_sts 0 0 0 0 0 0 0 isrc1int2_src [7:0] 0000h r2880 (b40h) isrc2dec1mix input 1 source isrc2 dec1 mix_s ts 0 0 0 0 0 0 0 isrc2dec1_src [7:0] 0000h r2888 (b48h) isrc2dec2mix input 1 source isrc2 dec2 mix_s ts 0 0 0 0 0 0 0 isrc2dec2_src [7:0] 0000h r2912 (b60h) isrc2int1mix input 1 source isrc2i nt1mi x_sts 0 0 0 0 0 0 0 isrc2int1_src [7:0] 0000h r2920 (b68h) isrc2int2mix input 1 source isrc2i nt2mi x_sts 0 0 0 0 0 0 0 isrc2int2_src [7:0] 0000h r3072 (c00h) gpio1 ctrl gp1_ dir gp1_p u gp1_p d 0 gp1_l vl gp1_p ol gp1_ op_c fg gp1_ db 0 gp1_fn [6:0] a101h r3073 (c01h) gpio2 ctrl gp2_ dir gp2_p u gp2_p d 0 gp2_l vl gp2_p ol gp2_ op_c fg gp2_ db 0 gp2_fn [6:0] a101h r3074 (c02h) gpio3 ctrl gp3_ dir gp3_p u gp3_p d 0 gp3_l vl gp3_p ol gp3_ op_c fg gp3_ db 0 gp3_fn [6:0] a101h r3075 (c03h) gpio4 ctrl gp4_ dir gp4_p u gp4_p d 0 gp4_l vl gp4_p ol gp4_ op_c fg gp4_ db 0 gp4_fn [6:0] a101h
production data WM5102 w pd, may 2013, rev 4.0 287 reg name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 default r3076 (c04h) gpio5 ctrl gp5_ dir gp5_p u gp5_p d 0 gp5_l vl gp5_p ol gp5_ op_c fg gp5_ db 0 gp5_fn [6:0] a101h r3087 (c0fh) irq ctrl 1 0 0 0 0 0 irq_p ol irq_o p_cf g 0 0 0 0 0 0 0 0 0 0400h r3088 (c10h) gpio debounce config gp_dbtime [3:0] 0 0 0 0 0 0 0 0 0 0 0 0 1000h r3104 (c20h) misc pad ctrl 1 ldo1 ena_ pd 0 mclk 2_pd 0 0 0 0 0 0 0 0 0 0 0 rese t_pu 0 8002h r3105 (c21h) misc pad ctrl 2 0 0 0 mclk 1_pd 0 0 0 micd_ pd 0 0 0 0 0 0 0 addr _pd 0001h r3106 (c22h) misc pad ctrl 3 0 0 0 0 0 0 0 0 0 0 0 0 0 dmic dat3_ pd dmic dat2_ pd dmic dat1_ pd 0000h r3107 (c23h) misc pad ctrl 4 0 0 0 0 0 0 0 0 0 0 aif1l rclk_ pu aif1l rclk_ pd aif1b clk_p u aif1b clk_p d aif1r xdat_ pu aif1r xdat_ pd 0000h r3108 (c24h) misc pad ctrl 5 0 0 0 0 0 0 0 0 0 0 aif2l rclk_ pu aif2l rclk_ pd aif2b clk_p u aif2b clk_p d aif2r xdat_ pu aif2r xdat_ pd 0000h r3109 (c25h) misc pad ctrl 6 0 0 0 0 0 0 0 0 0 0 aif3l rclk_ pu aif3l rclk_ pd aif3b clk_p u aif3b clk_p d aif3r xdat_ pu aif3r xdat_ pd 0000h r3328 (d00h) interrupt status 1 0 0 0 0 0 0 0 0 0 0 0 0 gp4_e int1 gp3_e int1 gp2_e int1 gp1_e int1 0000h r3329 (d01h) interrupt status 2 0 0 0 0 0 0 0 dsp1_ ram_ rdy_ eint1 0 0 0 0 0 0 dsp_i rq2_ eint1 dsp_i rq1_ eint1 0000h r3330 (d02h) interrupt status 3 spk_s hutd own_ warn _eint 1 spk_s hutd own_ eint1 hpde t_ein t1 micde t_ein t1 wseq _don e_ein t1 0 drc1_ sig_d et_ei nt1 asrc 2_loc k_ein t1 asrc 1_loc k_ein t1 unde rclo cked _eint 1 over cloc ked_ eint1 0 fll2_ lock _eint 1 fll1_ lock _eint 1 clkg en_e rr_ei nt1 clkg en_e rr_a sync _eint 1 0000h r3331 (d03h) interrupt status 4 asrc _cfg_ err_ eint1 aif3_ err_ eint1 aif2_ err_ eint1 aif1_ err_ eint1 ctrli f_er r_ein t1 mixer _dro pped _sam ple_e int1 asyn c_clk _ena_ low_ eint1 sysc lk_en a_lo w_ein t1 isrc1 _cfg_ err_ eint1 isrc2 _cfg_ err_ eint1 0 0 0 0 0 0 0000h r3332 (d04h) interrupt status 5 0 0 0 0 0 0 0 boot _don e_ein t1 dcs_ dac_ done _eint 1 dcs_ hp_d one_ eint1 0 0 0 0 fll2_ cloc k_ok_ eint1 fll1_ cloc k_ok_ eint1 0000h r3336 (d08h) interrupt status 1 mask 0 0 0 0 0 0 0 0 0 0 0 0 im_gp 4_ein t1 im_gp 3_ein t1 im_gp 2_ein t1 im_gp 1_ein t1 000fh r3337 (d09h) interrupt status 2 mask 0 0 0 0 0 0 0 im_ds p1_ra m_rd y_ein t1 0 0 0 0 0 0 im_ds p_irq 2_ein t1 im_ds p_irq 1_ein t1 0103h
WM5102 production data w pd, may 2013, rev 4.0 288 reg name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 default r3338 (d0ah) interrupt status 3 mask im_sp k_sh utdo wn_w arn_ eint1 im_sp k_sh utdo wn_ei nt1 im_hp det_e int1 im_mi cdet _eint 1 im_w seq_ done _eint 1 0 im_dr c1_si g_de t_ein t1 im_as rc2_l ock_ eint1 im_as rc1_l ock_ eint1 im_un derc lock ed_ei nt1 im_ov ercl ocke d_ein t1 0 im_fl l2_lo ck_ei nt1 im_fl l1_lo ck_ei nt1 im_cl kgen _err_ eint1 im_cl kgen _err_ asyn c_ein t1 fbefh r3339 (d0bh) interrupt status 4 mask im_as rc_c fg_e rr_ei nt1 im_aif 3_err _eint 1 im_aif 2_err _eint 1 im_aif 1_err _eint 1 im_ct rlif_ err_ eint1 im_mi xer_ drop ped_ samp le_ei nt1 im_as ync_ clk_e na_l ow_ei nt1 im_sy sclk_ ena_l ow_ei nt1 im_is rc1_c fg_e rr_ei nt1 im_is rc2_c fg_e rr_ei nt1 0 0 0 0 0 0 ffc0h r3340 (d0ch) interrupt status 5 mask 1 1 1 1 1 1 1 im_bo ot_d one_ eint1 im_dc s_da c_do ne_ei nt1 im_dc s_hp_ done _eint 1 0 0 0 0 im_fl l2_cl ock_ ok_ei nt1 im_fl l1_cl ock_ ok_ei nt1 fec3h r3343 (d0fh) interrupt control 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 im_ir q1 0000h r3344 (d10h) irq2 status 1 0 0 0 0 0 0 0 0 0 0 0 0 gp4_e int2 gp3_e int2 gp2_e int2 gp1_e int2 0000h r3345 (d11h) irq2 status 2 0 0 0 0 0 0 0 dsp1_ ram_ rdy_ eint2 0 0 0 0 0 0 dsp_i rq2_ eint2 dsp_i rq1_ eint2 0000h r3346 (d12h) irq2 status 3 spk_s hutd own_ warn _eint 2 spk_s hutd own_ eint2 hpde t_ein t2 micde t_ein t2 wseq _don e_ein t2 0 drc1_ sig_d et_ei nt2 asrc 2_loc k_ein t2 asrc 1_loc k_ein t2 unde rclo cked _eint 2 over cloc ked_ eint2 0 fll2_ lock _eint 2 fll1_ lock _eint 2 clkg en_e rr_ei nt2 clkg en_e rr_a sync _eint 2 0000h r3347 (d13h) irq2 status 4 asrc _cfg_ err_ eint2 aif3_ err_ eint2 aif2_ err_ eint2 aif1_ err_ eint2 ctrli f_er r_ein t2 mixer _dro pped _sam ple_e int2 asyn c_clk _ena_ low_ eint2 sysc lk_en a_lo w_ein t2 isrc1 _cfg_ err_ eint2 isrc2 _cfg_ err_ eint2 0 0 0 0 0 0 0000h r3348 (d14h) irq2 status 5 0 0 0 0 0 0 0 boot _don e_ein t2 dcs_ dac_ done _eint 2 dcs_ hp_d one_ eint2 0 0 0 0 fll2_ cloc k_ok_ eint2 fll1_ cloc k_ok_ eint2 0000h r3352 (d18h) irq2 status 1 mask 0 0 0 0 0 0 0 0 0 0 0 0 im_gp 4_ein t2 im_gp 3_ein t2 im_gp 2_ein t2 im_gp 1_ein t2 000fh r3353 (d19h) irq2 status 2 mask 0 0 0 0 0 0 0 im_ds p1_ra m_rd y_ein t2 0 0 0 0 0 0 im_ds p_irq 2_ein t2 im_ds p_irq 1_ein t2 0103h r3354 (d1ah) irq2 status 3 mask im_sp k_sh utdo wn_w arn_ eint2 im_sp k_sh utdo wn_ei nt2 im_hp det_e int2 im_mi cdet _eint 2 im_w seq_ done _eint 2 0 im_dr c1_si g_de t_ein t2 im_as rc2_l ock_ eint2 im_as rc1_l ock_ eint2 im_un derc lock ed_ei nt2 im_ov ercl ocke d_ein t2 0 im_fl l2_lo ck_ei nt2 im_fl l1_lo ck_ei nt2 im_cl kgen _err_ eint2 im_cl kgen _err_ asyn c_ein t2 ffefh
production data WM5102 w pd, may 2013, rev 4.0 289 reg name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 default r3355 (d1bh) irq2 status 4 mask im_as rc_c fg_e rr_ei nt2 im_aif 3_err _eint 2 im_aif 2_err _eint 2 im_aif 1_err _eint 2 im_ct rlif_ err_ eint2 im_mi xer_ drop ped_ samp le_ei nt2 im_as ync_ clk_e na_l ow_ei nt2 im_sy sclk_ ena_l ow_ei nt2 im_is rc1_c fg_e rr_ei nt2 im_is rc2_c fg_e rr_ei nt2 0 0 0 0 0 0 ffc0h r3356 (d1ch) irq2 status 5 mask 1 1 1 1 1 1 1 im_bo ot_d one_ eint2 im_dc s_da c_do ne_ei nt2 im_dc s_hp_ done _eint 2 0 0 0 0 im_fl l2_cl ock_ ok_ei nt2 im_fl l1_cl ock_ ok_ei nt2 fec3h r3359 (d1fh) irq2 control 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 im_ir q2 0000h r3360 (d20h) interrupt raw status 2 0 0 0 0 0 0 0 dsp1_ ram_ rdy_ sts 0 0 0 0 0 0 dsp_i rq2_ sts dsp_i rq1_ sts 0000h r3361 (d21h) interrupt raw status 3 spk_s hutd own_ warn _sts spk_s hutd own_ sts 0 0 wseq _don e_sts 0 drc1_ sig_d et_st s asrc 2_loc k_sts asrc 1_loc k_sts unde rclo cked _sts over cloc ked_ sts 0 fll2_ lock _sts fll1_ lock _sts clkg en_e rr_s ts clkg en_e rr_a sync _sts 0000h r3362 (d22h) interrupt raw status 4 asrc _cfg_ err_ sts aif3_ err_ sts aif2_ err_ sts aif1_ err_ sts ctrli f_er r_sts mixer _dro pped _sam ple_s ts asyn c_clk _ena_ low_ sts sysc lk_en a_lo w_st s isrc1 _cfg_ err_ sts isrc2 _cfg_ err_ sts 0 0 0 0 0 0 0000h r3363 (d23h) interrupt raw status 5 0 0 0 0 0 0 0 boot _don e_sts dcs_ dac_ done _sts dcs_ hp_d one_ sts 0 0 0 0 fll2_ cloc k_ok_ sts fll1_ cloc k_ok_ sts 0000h r3364 (d24h) interrupt raw status 6 0 0 pwm_ over cloc ked_ sts fx_c ore_ over cloc ked_ sts 0 dac_ sys_ over cloc ked_ sts dac_ warp _ove rclo cked _sts adc_ over cloc ked_ sts mixer _ove rclo cked _sts aif3_ asyn c_ov ercl ocke d_sts aif2_ asyn c_ov ercl ocke d_sts aif1_ asyn c_ov ercl ocke d_sts aif3_ sync _ove rclo cked _sts aif2_ sync _ove rclo cked _sts aif1_ sync _ove rclo cked _sts pad_ ctrl_ over cloc ked_ sts 0000h r3365 (d25h) interrupt raw status 7 slimb us_s ubsy s_ov ercl ocke d_sts slimb us_a sync _ove rclo cked _sts slimb us_s ync_ over cloc ked_ sts asrc _asy nc_s ys_o verc lock ed_st s asrc _asy nc_w arp_ over cloc ked_ sts asrc _syn c_sy s_ov ercl ocke d_sts asrc _syn c_wa rp_o verc lock ed_st s 0 0 0 0 0 dsp1_ over cloc ked_ sts 0 isrc2 _ove rclo cked _sts isrc1 _ove rclo cked _sts 0000h r3366 (d26h) interrupt raw status 8 0 0 0 0 0 aif3_ unde rclo cked _sts aif2_ unde rclo cked _sts aif1_ unde rclo cked _sts 0 isrc2 _und ercl ocke d_sts isrc1 _und ercl ocke d_sts fx_u nder cloc ked_ sts asrc _und ercl ocke d_sts dac_ unde rclo cked _sts adc_ unde rclo cked _sts mixer _und ercl ocke d_sts 0000h r3392 (d40h) irq pin status 0 0 0 0 0 0 0 0 0 0 0 0 0 0 irq2_ sts irq1_ sts 0000h r3408 (d50h) aod wkup and trig 0 0 0 0 0 0 0 0 micd_ clam p_fal l_tri g_st s micd_ clam p_ris e_tri g_st s gp5_f all_t rig_s ts gp5_ rise_ trig_ sts jd1_f all_t rig_s ts jd1_r ise_t rig_s ts 0 0 0000h
WM5102 production data w pd, may 2013, rev 4.0 290 reg name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 default r3409 (d51h) aod irq1 0 0 0 0 0 0 0 0 micd_ clam p_fal l_ein t1 micd_ clam p_ris e_ein t1 gp5_f all_e int1 gp5_ rise_ eint1 jd1_f all_e int1 jd1_r ise_ei nt1 0 0 0000h r3410 (d52h) aod irq2 0 0 0 0 0 0 0 0 micd_ clam p_fal l_ein t2 micd_ clam p_ris e_ein t2 gp5_f all_e int2 gp5_ rise_ eint2 jd1_f all_e int2 jd1_r ise_ei nt2 0 0 0000h r3411 (d53h) aod irq mask irq1 0 0 0 0 0 0 0 0 im_mi cd_cl amp_ fall_ eint1 im_mi cd_cl amp_ rise_ eint1 im_gp 5_fal l_ein t1 im_gp 5_ris e_ein t1 im_jd 1_fal l_ein t1 im_jd 1_ris e_ein t1 0 0 003ch r3412 (d54h) aod irq mask irq2 0 0 0 0 0 0 0 0 im_mi cd_cl amp_ fall_ eint2 im_mi cd_cl amp_ rise_ eint2 im_gp 5_fal l_ein t2 im_gp 5_ris e_ein t2 im_jd 1_fal l_ein t2 im_jd 1_ris e_ein t2 0 0 003ch r3413 (d55h) aod irq raw status 0 0 0 0 0 0 0 0 0 0 0 0 micd_ clam p_sts gp5_s ts 0 jd1_s ts 0000h r3414 (d56h) jack detect debounce 0 0 0 0 0 0 0 0 0 0 0 0 micd_ clam p_db 0 0 jd1_d b 0000h r3584 (e00h) fx_ctrl1 0 fx_rate [3:0] 0 0 0 0 0 0 0 0 0 0 0 0000h r3585 (e01h) fx_ctrl2 fx_sts [11:0] 0 0 0 0 0000h r3600 (e10h) eq1_1 eq1_b1_gain [4:0] eq1_b2_gain [4:0] eq1_b3_gain [4:0] eq1_e na 6318h r3601 (e11h) eq1_2 eq1_b4_gain [4:0] eq1_b5_gain [4:0] 0 0 0 0 0 eq1_ mode 6300h r3602 (e12h) eq1_3 eq1_b1_a [15:0] 0fc8h r3603 (e13h) eq1_4 eq1_b1_b [15:0] 03feh r3604 (e14h) eq1_5 eq1_b1_pg [15:0] 00e0h r3605 (e15h) eq1_6 eq1_b2_a [15:0] 1ec4h r3606 (e16h) eq1_7 eq1_b2_b [15:0] f136h r3607 (e17h) eq1_8 eq1_b2_c [15:0] 0409h r3608 (e18h) eq1_9 eq1_b2_pg [15:0] 04cch r3609 (e19h) eq1_10 eq1_b3_a [15:0] 1c9bh r3610 (e1ah) eq1_11 eq1_b3_b [15:0] f337h r3611 (e1bh) eq1_12 eq1_b3_c [15:0] 040bh r3612 (e1ch) eq1_13 eq1_b3_pg [15:0] 0cbbh r3613 (e1dh) eq1_14 eq1_b4_a [15:0] 16f8h r3614 (e1eh) eq1_15 eq1_b4_b [15:0] f7d9h r3615 (e1fh) eq1_16 eq1_b4_c [15:0] 040ah r3616 (e20h) eq1_17 eq1_b4_pg [15:0] 1f14h r3617 (e21h) eq1_18 eq1_b5_a [15:0] 058ch r3618 (e22h) eq1_19 eq1_b5_b [15:0] 0563h r3619 (e23h) eq1_20 eq1_b5_pg [15:0] 4000h r3620 (e24h) eq1_21 eq1_b1_c [15:0] 0b75h r3622 (e26h) eq2_1 eq2_b1_gain [4:0] eq2_b2_gain [4:0] eq2_b3_gain [4:0] eq2_e na 6318h r3623 (e27h) eq2_2 eq2_b4_gain [4:0] eq2_b5_gain [4:0] 0 0 0 0 0 eq2_ mode 6300h r3624 (e28h) eq2_3 eq2_b1_a [15:0] 0fc8h
production data WM5102 w pd, may 2013, rev 4.0 291 reg name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 default r3625 (e29h) eq2_4 eq2_b1_b [15:0] 03feh r3626 (e2ah) eq2_5 eq2_b1_pg [15:0] 00e0h r3627 (e2bh) eq2_6 eq2_b2_a [15:0] 1ec4h r3628 (e2ch) eq2_7 eq2_b2_b [15:0] f136h r3629 (e2dh) eq2_8 eq2_b2_c [15:0] 0409h r3630 (e2eh) eq2_9 eq2_b2_pg [15:0] 04cch r3631 (e2fh) eq2_10 eq2_b3_a [15:0] 1c9bh r3632 (e30h) eq2_11 eq2_b3_b [15:0] f337h r3633 (e31h) eq2_12 eq2_b3_c [15:0] 040bh r3634 (e32h) eq2_13 eq2_b3_pg [15:0] 0cbbh r3635 (e33h) eq2_14 eq2_b4_a [15:0] 16f8h r3636 (e34h) eq2_15 eq2_b4_b [15:0] f7d9h r3637 (e35h) eq2_16 eq2_b4_c [15:0] 040ah r3638 (e36h) eq2_17 eq2_b4_pg [15:0] 1f14h r3639 (e37h) eq2_18 eq2_b5_a [15:0] 058ch r3640 (e38h) eq2_19 eq2_b5_b [15:0] 0563h r3641 (e39h) eq2_20 eq2_b5_pg [15:0] 4000h r3642 (e3ah) eq2_21 eq2_b1_c [15:0] 0b75h r3644 (e3ch) eq3_1 eq3_b1_gain [4:0] eq3_b2_gain [4:0] eq3_b3_gain [4:0] eq3_e na 6318h r3645 (e3dh) eq3_2 eq3_b4_gain [4:0] eq3_b5_gain [4:0] 0 0 0 0 0 eq3_ mode 6300h r3646 (e3eh) eq3_3 eq3_b1_a [15:0] 0fc8h r3647 (e3fh) eq3_4 eq3_b1_b [15:0] 03feh r3648 (e40h) eq3_5 eq3_b1_pg [15:0] 00e0h r3649 (e41h) eq3_6 eq3_b2_a [15:0] 1ec4h r3650 (e42h) eq3_7 eq3_b2_b [15:0] f136h r3651 (e43h) eq3_8 eq3_b2_c [15:0] 0409h r3652 (e44h) eq3_9 eq3_b2_pg [15:0] 04cch r3653 (e45h) eq3_10 eq3_b3_a [15:0] 1c9bh r3654 (e46h) eq3_11 eq3_b3_b [15:0] f337h r3655 (e47h) eq3_12 eq3_b3_c [15:0] 040bh r3656 (e48h) eq3_13 eq3_b3_pg [15:0] 0cbbh r3657 (e49h) eq3_14 eq3_b4_a [15:0] 16f8h r3658 (e4ah) eq3_15 eq3_b4_b [15:0] f7d9h r3659 (e4bh) eq3_16 eq3_b4_c [15:0] 040ah r3660 (e4ch) eq3_17 eq3_b4_pg [15:0] 1f14h r3661 (e4dh) eq3_18 eq3_b5_a [15:0] 058ch r3662 (e4eh) eq3_19 eq3_b5_b [15:0] 0563h r3663 (e4fh) eq3_20 eq3_b5_pg [15:0] 4000h r3664 (e50h) eq3_21 eq3_b1_c [15:0] 0b75h r3666 (e52h) eq4_1 eq4_b1_gain [4:0] eq4_b2_gain [4:0] eq4_b3_gain [4:0] eq4_e na 6318h r3667 (e53h) eq4_2 eq4_b4_gain [4:0] eq4_b5_gain [4:0] 0 0 0 0 0 eq4_ mode 6300h r3668 (e54h) eq4_3 eq4_b1_a [15:0] 0fc8h r3669 (e55h) eq4_4 eq4_b1_b [15:0] 03feh r3670 (e56h) eq4_5 eq4_b1_pg [15:0] 00e0h r3671 (e57h) eq4_6 eq4_b2_a [15:0] 1ec4h r3672 (e58h) eq4_7 eq4_b2_b [15:0] f136h r3673 (e59h) eq4_8 eq4_b2_c [15:0] 0409h
WM5102 production data w pd, may 2013, rev 4.0 292 reg name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 default r3674 (e5ah) eq4_9 eq4_b2_pg [15:0] 04cch r3675 (e5bh) eq4_10 eq4_b3_a [15:0] 1c9bh r3676 (e5ch) eq4_11 eq4_b3_b [15:0] f337h r3677 (e5dh) eq4_12 eq4_b3_c [15:0] 040bh r3678 (e5eh) eq4_13 eq4_b3_pg [15:0] 0cbbh r3679 (e5fh) eq4_14 eq4_b4_a [15:0] 16f8h r3680 (e60h) eq4_15 eq4_b4_b [15:0] f7d9h r3681 (e61h) eq4_16 eq4_b4_c [15:0] 040ah r3682 (e62h) eq4_17 eq4_b4_pg [15:0] 1f14h r3683 (e63h) eq4_18 eq4_b5_a [15:0] 058ch r3684 (e64h) eq4_19 eq4_b5_b [15:0] 0563h r3685 (e65h) eq4_20 eq4_b5_pg [15:0] 4000h r3686 (e66h) eq4_21 eq4_b1_c [15:0] 0b75h r3712 (e80h) drc1 ctrl1 drc1_sig_det_rms [4:0] drc1_sig_de t_pk [1:0] drc1_ ng_e na drc1_ sig_d et_m ode drc1_ sig_d et drc1_ knee 2_op_ ena drc1_ qr drc1_ antic lip drc1_ wseq _sig_ det_e na drc1l _ena drc1 r_en a 0018h r3713 (e81h) drc1 ctrl2 0 0 0 drc1_atk [3:0] drc1_dcy [3:0 ] drc1_mingain [2:0] drc1_maxga in [1:0] 0933h r3714 (e82h) drc1 ctrl3 drc1_ng_mingain [3:0] drc1_ng_ex p [1:0] drc1_qr_th r [1:0] drc1_qr_dc y [1:0] drc1_hi_comp [2:0] drc1_lo_comp [2:0] 0018h r3715 (e83h) drc1 ctrl4 0 0 0 0 0 drc1_knee_ip [5:0] drc1_knee_op [4:0] 0000h r3716 (e84h) drc1 ctrl5 0 0 0 0 0 0 drc1_knee2_ip [4:0] drc1_knee2_op [4:0] 0000h r3776 (ec0h) hplpf1_1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 lhpf1 _mod e lhpf1 _ena 0000h r3777 (ec1h) hplpf1_2 lhpf1_coeff [15:0] 0000h r3780 (ec4h) hplpf2_1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 lhpf2 _mod e lhpf2 _ena 0000h r3781 (ec5h) hplpf2_2 lhpf2_coeff [15:0] 0000h r3784 (ec8h) hplpf3_1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 lhpf3 _mod e lhpf3 _ena 0000h r3785 (ec9h) hplpf3_2 lhpf3_coeff [15:0] 0000h r3788 (ecch) hplpf4_1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 lhpf4 _mod e lhpf4 _ena 0000h r3789 (ecdh) hplpf4_2 lhpf4_coeff [15:0] 0000h r3808 (ee0h) asrc_enable 0 0 0 0 0 0 0 0 0 0 0 0 asrc 2l_en a asrc 2r_en a asrc 1l_en a asrc 1r_en a 0000h r3809 (ee1h) asrc_status 0 0 0 0 0 0 0 0 0 0 0 0 asrc 2l_en a_sts asrc 2r_en a_sts asrc 1l_en a_sts asrc 1r_en a_sts 0000h r3810 (ee2h) asrc_rate1 0 asrc_rate1 [3:0] 0 0 0 0 0 0 0 0 0 0 0 0000h r3811 (ee3h) asrc_rate2 0 asrc_rate2 [3:0] 0 0 0 0 0 0 0 0 0 0 0 0400h r3824 (ef0h) isrc 1 ctrl 1 0 isrc1_fsh [3:0] 0 0 0 0 0 0 0 0 0 0 0 0000h r3825 (ef1h) isrc 1 ctrl 2 0 isrc1_fsl [3:0] 0 0 0 0 0 0 0 0 0 0 0 0000h r3826 (ef2h) isrc 1 ctrl 3 isrc1 _int1 _ena isrc1 _int2 _ena 0 0 0 0 isrc1 _dec1 _ena isrc1 _dec2 _ena 0 0 0 0 0 0 0 isrc1 _not ch_e na 0000h r3827 (ef3h) isrc 2 ctrl 1 0 isrc2_fsh [3:0] 0 0 0 0 0 0 0 0 0 0 0 0000h
production data WM5102 w pd, may 2013, rev 4.0 293 reg name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 default r3828 (ef4h) isrc 2 ctrl 2 0 isrc2_fsl [3:0] 0 0 0 0 0 0 0 0 0 0 0 0000h r3829 (ef5h) isrc 2 ctrl 3 isrc2 _int1 _ena isrc2 _int2 _ena 0 0 0 0 isrc2 _dec1 _ena isrc2 _dec2 _ena 0 0 0 0 0 0 0 isrc2 _not ch_e na 0000h r4352 (1100h) dsp1 control 1 0 dsp1_rate [3:0] 0 0 0 0 0 0 dsp1_ mem_ ena 0 dsp1_ sys_e na dsp1_ core _ena dsp1_ star t 0010h r4353 (1101h) dsp1 clocking 1 0 0 0 0 0 0 0 0 0 0 0 0 0 dsp1_clk_sel [2:0] 0000h r4356 (1104h) dsp1 status 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 dsp1_ ram_ rdy 0000h r4357 (1105h) dsp1 status 2 dsp1_ ping_ full dsp1_ pong _full 0 0 0 0 0 0 dsp1_wdma_active_channels [7:0] 0000h r4368 (1110h) dsp1 wdma buffer 1 dsp1_start_address_wdma _buffer_0 [15:0] 0000h r4369 (1111h) dsp1 wdma buffer 2 dsp1_start_address_wdma _buffer_1 [15:0] 0000h r4370 (1112h) dsp1 wdma buffer 3 dsp1_start_address_wdma _buffer_2 [15:0] 0000h r4371 (1113h) dsp1 wdma buffer 4 dsp1_start_address_wdma _buffer_3 [15:0] 0000h r4372 (1114h) dsp1 wdma buffer 5 dsp1_start_address_wdma _buffer_4 [15:0] 0000h r4373 (1115h) dsp1 wdma buffer 6 dsp1_start_address_wdma _buffer_5 [15:0] 0000h r4374 (1116h) dsp1 wdma buffer 7 dsp1_start_address_wdma _buffer_6 [15:0] 0000h r4375 (1117h) dsp1 wdma buffer 8 dsp1_start_address_wdma _buffer_7 [15:0] 0000h r4384 (1120h) dsp1 rdma buffer 1 dsp1_start_address_rdma_ buffer_0 [15:0] 0000h r4385 (1121h) dsp1 rdma buffer 2 dsp1_start_address_rdma_ buffer_1 [15:0] 0000h r4386 (1122h) dsp1 rdma buffer 3 dsp1_start_address_rdma_ buffer_2 [15:0] 0000h r4387 (1123h) dsp1 rdma buffer 4 dsp1_start_address_rdma_ buffer_3 [15:0] 0000h r4388 (1124h) dsp1 rdma buffer 5 dsp1_start_address_rdma_ buffer_4 [15:0] 0000h r4389 (1125h) dsp1 rdma buffer 6 dsp1_start_address_rdma_ buffer_5 [15:0] 0000h r4400 (1130h) dsp1 wdma config 1 0 0 dsp1_wdma_buffer_length [13:0] 0000h r4401 (1131h) dsp1 wdma config 2 0 0 0 0 0 0 0 0 dsp1_wdma_channel_enable [7:0] 0000h r4404 (1134h) dsp1 rdma config 1 0 0 0 0 0 0 0 0 0 0 dsp1_rdma_channel_enable [5:0] 0000h r4416 (1140h) dsp1 scratch 0 dsp1_scratch_0 [15:0] 0000h r4417 (1141h) dsp1 scratch 1 dsp1_scratch_1 [15:0] 0000h r4418 (1142h) dsp1 scratch 2 dsp1_scratch_2 [15:0] 0000h r4419 (1143h) dsp1 scratch 3 dsp1_scratch_3 [15:0] 0000h control write sequencer memory r12288 (3000h) wseq sequence 1 wseq_data_width0 [2:0] wseq_addr0 [12:0] 0225h
WM5102 production data w pd, may 2013, rev 4.0 294 reg name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 default r12289 (3001h) wseq sequence 2 wseq_delay0 [3:0] wseq_data_start0 [3:0] wseq_data0 [7:0] 0001h r12290 (3002h) wseq sequence 3 wseq_data_width1 [2:0] wseq_addr1 [12:0] 0000h r12291 (3003h) wseq sequence 4 wseq_delay1 [3:0] wseq_data_start1 [3:0] wseq_data1 [7:0] 0003h (similar for wseq index 2 ? 254) r12798 (31feh) wseq sequence 511 wseq_data_width2 55 [2:0] wseq_addr255 [12:0] 0000h r12799 (31ffh) wseq sequence 512 wseq_delay255 [3:0] wseq_data_start255 [3:0] wseq_data255 [7:0] 0000h dsp1 firmware memory r1048576 (10_0000h) dsp1pm0 0 0 0 0 0 0 0 0 dsp1_pm_0 [39:32] 0000h r1048577 (10_0001h) dsp1pm1 dsp1_pm_0 [31:16] 0000h r1048578 (10_0002h) dsp1pm2 dsp1_pm_0 [15:0] 0000h r1048579 (10_0003h) dsp1pm3 0 0 0 0 0 0 0 0 dsp1_pm_1 [39:32] 0000h r1048580 (10_0004h) dsp1pm4 dsp1_pm_1 [31:16] 0000h r1048581 (10_0005h) dsp1pm5 dsp1_pm_1 [15:0] 0000h (similar for dsp1 program memory 2 ? 8190) r1073149 (10_5ffdh) dsp1pm024573 0 0 0 0 0 0 0 0 dsp1_pm_8191 [39:32] 0000h r1073150 (10_5ffeh) dsp1pm24574 dsp1_pm_8191 [31:16] 0000h r1073151 (10_5fffh) dsp1pm24575 dsp1_pm_8191 [15:0] 0000h r1572864 (18_0000h) dsp1zm0 0 0 0 0 0 0 0 0 dsp1_zm_0 [23:16] 0000h r1572865 (18_0001h) dsp1zm1 dsp1_zm_0 [15:0] 0000h r1572866 (18_0002h) dsp1zm2 0 0 0 0 0 0 0 0 dsp1_zm_1 [23:16] 0000h r1572867 (18_0003h) dsp1zm3 dsp1_zm_1 [15:0] 0000h (similar for dsp1 coefficient memory 2 ? 1022) r1574910 (18_07feh) dsp1zm2046 0 0 0 0 0 0 0 0 dsp1_zm_1023 [23:16] 0000h r1574911 (18_07ffh) dsp1zm2047 dsp1_zm_1023 [15:0] 0000h r1638400 (19_0000h) dsp1xm0 0 0 0 0 0 0 0 0 dsp1_xm_0 [23:16] 0000h r1638401 (19_0001h) dsp1xm1 dsp1_xm_0 [15:0] 0000h r1638402 (19_0002h) dsp1xm2 0 0 0 0 0 0 0 0 dsp1_xm_1 [23:16] 0000h r1638403 (19_0003h) dsp1xm3 dsp1_xm_1 [15:0] 0000h
production data WM5102 w pd, may 2013, rev 4.0 295 reg name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 default (similar for dsp1 x data memory 2 ? 9214) r1656830 (19_47feh) dsp1xm18430 0 0 0 0 0 0 0 0 dsp1_xm_9215 [23:16] 0000h r1656831 (19_47ffh) dsp1xm18431 dsp1_xm_9215 [15:0] 0000h r1736704 (1a_8000h) dsp1ym0 0 0 0 0 0 0 0 0 dsp1_ym_0 [23:16] 0000h r1736705 (1a_8001h) dsp1ym1 dsp1_ym_0 [15:0] 0000h r1736706 (1a_8002h) dsp1ym2 0 0 0 0 0 0 0 0 dsp1_ym_1 [23:16] 0000h r1736707 (1a_8003h) dsp1ym3 dsp1_ym_1 [15:0] 0000h (similar for dsp1 y data memory 2 ? 3070) r1742846 (1a_97feh) dsp1ym6142 0 0 0 0 0 0 0 0 dsp1_ym_3071 [23:16] 0000h r1742847 (1a_97ffh) dsp1ym6143 dsp1_ym_3071 [15:0] 0000h
WM5102 production data w pd, may 2013, rev 4.0 296 applications information recommended external components analogue input paths the WM5102 provides up to 6 analogue audio input paths. each of these inputs is referenced to the internal dc reference, vmid. a dc blocking capacit or is required for each analogue input pin used in the target application. the choice of capacitor is determined by the filter that is formed between that capacitor and the impedance of the input pin. the circuit is illustrated in figure 78. figure 78 audio input path dc blocking capacitor in accordance with the WM5102 input pin resistanc e (see ?electrical characteristics?), it is recommended that a 1 ? f capacitance for all input connections will give good results in most cases, with a 3db cut-off frequency around 13hz. ceramic capacitors are suitable, but care must be taken to ensure t he desired capacitance is maintained at the avdd operating voltage. also, ce ramic capacitors may show microphonic effects, where vibrations and mechanical condi tions give rise to electrical signals. this is particularly problematic for microphone input paths w here a large signal gain is required. a single capacitor is required fo r a single-ended line or microphone input connection. for a differential input connection, a dc blocking capacit or is required on both input pins. the external connections for single-ended and differential microphones, incorporating the WM5102 microphone bias circuit, are shown la ter in the ?microphone bias circ uit? section - see figure 79. digital microphone input paths the WM5102 provides up to 6 digital microphone input paths; two channels of audio data can be multiplexed on each of the dmicdatn pins. each of these stereo pairs is clo cked using the respective dmicclkn pin. the external connections for di gital microphones, incorporating the WM5102 microphone bias circuit, are shown later in the ?microphone bias circuit? section - see figure 80. ceramic decoupling capacitors for the digital micr ophones may be required - refer to the specific recommendations for the application microphone(s). when two microphones are connected to a single dm icdat pin, the microphones must be configured to ensure that the left mic transmits a data bit w hen dmicclk is high, and the right mic transmits a data bit when dmicclk is low. the WM5102 samples the digital microphone data at the end of each dmicclk phase. each microphone must tri-stat e its data output when the other microphone is transmitting. integrated pull-down resistors c an be enabled on the dmicdat pins if required. the voltage reference for each digital microphone interf ace is selectable. it is important that the selected reference for the WM5102 interface is com patible with the applicable configuration of the external microphone. microphone bias circuit the WM5102 is designed to interface easily with up to 6 analogue or digital microphones.
production data WM5102 w pd, may 2013, rev 4.0 297 each microphone requires a bias current (elect ret condenser microphones) or voltage supply (silicon microphones); these can be provided by the micbi as1, micbias2 or micbias3 regulators on the WM5102. analogue microphones may be connected in single-ended or differential c onfigurations, as illustrated in figure 79. the differential configuration provi des better performance due to its rejection of common- mode noise; the single-ended method provides a reduction in external component count. a current-limiting resistor is required when using an electret condens er microphone (ecm). the resistance should be chosen according to t he minimum operating impedance of the microphone and micbias voltage so that the maximum bias current of the WM5102 is not exceeded. a 2.2k ? current-limiting resistor is recommended; this provides compatibility with a wide range of microphone components. figure 79 single-ended and differential analogue microphone connections digital microphone connection to the wm 5102 is illustrated in figure 80. ceramic decoupling capacitors for the digital micr ophones may be required - refer to the specific recommendations for the application microphone(s). figure 80 digital microphone connection the micbias generators can each operate as a volt age regulator or in bypass mode. see ?charge pumps, regulators and voltage reference? for details of the micbias generators.
WM5102 production data w pd, may 2013, rev 4.0 298 in regulator mode, the micbias regulators ar e designed to operate without external decoupling capacitors. the regulators can be c onfigured to support a capacitive l oad if required (eg. for digital microphone supply decoupling). the compatible load conditions are detailed in the ?electrical characteristics? section. if the capacitive load on micbias1, micbias2 or micbias3 exceeds the s pecified conditions for regulator mode (eg. due to a decoupling capacitor or long pcb trace), then the respective generator must be configured in bypass mode. the maximum output current for each micbias n pin is noted in the ?electrical characteristics?. this limit must be observed on each micbias output, es pecially if more than one microphone is connected to a single micbias pin. note that the maximu m output current differs between regulator mode and bypass mode. the micbias output voltage can be adjust ed using register control in regulator mode. headphone/earpiece driver output path the WM5102 provides 2 stereo headphone and 1 mono earpi ece output drivers. these outputs are all ground-referenced, allowing direct connection to the external load(s). there is no requirement for dc blocking capacitors. in single-ended (default) configuration, t he headphone outputs comprise 4 independently controlled output channels, for up to 2 stereo headphone or line outputs. in mono (btl) mode, the headphone drivers support up to 2 differential outputs, su itable for a mono earpiece or hearing coil load. the headphone outputs incorporate a common mode, or ground loop, feedback path which provides rejection of system-related ground noise. the feedback pins must be connected to ground for normal operation of the headphone outputs. two alternate f eedback pins are configurable for the hpout1l and hpout1r drivers. the feedback pins should be connected to gnd clos e to the respective headphone jack, as illustrated in figure 81. in mono (differential) mode, t he feedback pin(s) should be connected to the ground plane that is physically closest to the earpiece output pcb tracks. the mono earpiece output is supported on the epo utp and epoutn pins. the output configuration is differential (btl), suitable for direct connec tion to an external earpiece or hearing coil load. typical headphone and earpiece connections are illustrated in figure 81. it is recommended to ensure that the electrical characteristics of t he pcb traces for each output pair are closely matched. this is particu larly important to matching the tw o traces of a differential (btl) output. figure 81 headphone and earpiece connection it is common for esd diodes to be wired to pins t hat link to external c onnectors. this provides protection from potentially harmful esd effects. in a typical application, esd diodes would be recommended for both headphone paths (hpout1 and hpout2), when used as external headphone or line output.
production data WM5102 w pd, may 2013, rev 4.0 299 the hpout1 and hpout2 outputs are ground-refer enced, and the respective voltages may swing between +1.8v and -1.8v. the esd diode configuration must be carefully chosen. the recommended esd diode configuration for thes e ground-referenced outputs is illustrated in figure 82. the ?back-to-back? arrangement is necessary in order to prevent clipping and distortion of the output signal. note that similar care is required when connecti ng the WM5102 outputs to external circuits that provide input path esd protection - the configuration on those input circuits must be correctly designed to accommodate ground-referenced signals. figure 82 esd diode configuration for external output connections speaker driver output path the WM5102 incorporates two class d speaker driver s, offering high amplifier efficiency at large signal levels. as the class d output is a pulse width modulated signal, the choice of speakers and tracking of signals is critical for ensuring good performance and reducing emi in this mode. the efficiency of the speaker drivers is affe cted by the series resistance between the WM5102 and the speaker (e.g. pcb track loss and inductor esr) as shown in figure 83. this resistance should be as low as possible to maximise efficiency. figure 83 speaker connection losses the class d output requires external filtering in order to recreate the audio signal. this may be implemented using a 2 nd order lc or 1 st order rc filter, or else may be achieved by using a loudspeaker whose internal inductance provides the required filter response. an lc or rc filter should be used if the loudspeaker characte ristics are unknown or unsuitable, or if the length of the
WM5102 production data w pd, may 2013, rev 4.0 300 loudspeaker connection is likely to lead to emi problems. in applications where it is necessary to provide class d filter components, a 2 nd order lc filter is the recommended solution as it provides more att enuation at higher frequencies and minimises power dissipated in the filter when compared to a first or der rc filter (lower esr). this maximises both rejection of unwanted switching frequencies and overa ll speaker efficiency. a suitable implementation is illustrated in figure 84. figure 84 class d output filter components a simple equivalent circuit of a l oudspeaker consists of a serially connected resistor and inductor, as shown in figure 85. this circuit provides a low pass filter for t he speaker output. if the loudspeaker characteristics are suitable, then the loudspeaker it self can be used in place of the filter components described earlier. this is know n as ?filterless? operation. figure 85 speaker equivalent circuit for filterless operation for filterless class d operation, it is important to ensure that a speaker wi th suitable inductance is chosen. for example, if we know the speaker impedance is 8 ? and the desired cut-off frequency is 20khz, then the optimum speaker inductance may be calculated as: 8 ? loudspeakers typically have an inductance in the range 20 ? h to 100 ? h, however, it should be noted that a loudspeaker inductance will not be cons tant across the relevant frequencies for class d operation (up to and beyond the class d switching frequency). care should be taken to ensure that the cut-off frequency of the loudspeaker?s filt ering is low enough to suppress the high frequency energy of the class d switching and, in so doing, to prevent speaker damage. the class d outputs of the WM5102 operate at much higher frequencies than is recommended for most speakers and it must be ensured that the cut-off frequency is low enough to protect the speaker.
production data WM5102 w pd, may 2013, rev 4.0 301 power supply / reference decoupling electrical coupling exists particu larly in digital logic systems where switching in one sub-system causes fluctuations on the power supply. this effect occurs bec ause the inductance of the power supply acts in opposition to the c hanges in current flow that are caused by the logic switching. the resultant variations (?spikes?) in the power supply voltage can cause ma lfunctions and unintentional behavior in other components. a decoupling (?bypa ss?) capacitor can be used as an energy storage component which will provide power to the decoupled circuit for the duration of these power supply variations, protecting it from malfunc tions that could otherwise arise. coupling also occurs in a lower frequency form w hen ripple is present on the power supply rail caused by changes in the load current or by limitations of the power supply regulation method. in audio components such as the WM5102, these variations can alter the performance of the signal path, leading to degradation in signal quality. a decoupling capac itor can be used to filter these effects, by presenting the ripple voltage with a low impedance path that does not affect the circuit to be decoupled. these coupling effects are addressed by plac ing a capacitor between the supply rail and the corresponding ground reference. in the case of sy stems comprising multiple power supply rails, decoupling should be provided on each rail. the recommended power supply and voltage refe rence decoupling capacitors for WM5102 are detailed below in table 117. power supply decoupling capacitor ldovdd, dbvdd1, dbvdd2, dbvdd3, avdd 0.1 ? f ceramic (see note) cpvdd 4.7 ? f ceramic micvdd 4.7 ? f ceramic dcvdd 4.7 ? f ceramic spkvddl, spkvddr 4.7 ? f ceramic vrefc 1.0 ? f ceramic table 117 power supply decoupling capacitors note: 0.1 ? f is required with 4.7 ? f a guide to the total required power rail capacitance. all decoupling capacitors should be placed as close as possibl e to the WM5102 device. the connection between agnd, the avdd decoupling capac itor and the main system ground should be made at a single point as close as po ssible to the agnd balls of the WM5102. due to the wide tolerance of many types of ceramic capacitors, care must be taken to ensure that the selected components provide the required capacit ance across the required temperature and voltage ranges in the intended application. for most applicati on the use of ceramic capacitors with capacitor dielectric x5r is recommended.
WM5102 production data w pd, may 2013, rev 4.0 302 charge pump components the WM5102 incorporates two charge pump circuits, identified as cp1 and cp2. cp1 generates the cp1voutp and cp1voutn supply rails for the ground-referenced headphone drivers; cp2 generates the cp2vout supply rail for the microphone bias (micbias) regulators. decoupling capacitors are required on each of the c harge pump outputs. a fly-back capacitor is also required for each charge pump. the recommended charge pump capacitors for WM5102 are detailed below in table 118. description capacitor cp1voutp decoupling requi red capacitance is 2.0 ? f at 2v. suitable component typically 4.7 ? f. cp1voutn decoupling requi red capacitance is 2.0 ? f at 2v. suitable component typically 4.7 ? f. cp1 fly-back (connect between cp1ca and cp1cb) required capacitance is 1.0 ? f at 2v. suitable component typically 2.2 ? f. cp2vout decoupling requir ed capacitance is 1.0 ? f at 3.6v. suitable component typically 4.7 ? f. cp2 fly-back (connect between cp2ca and cp2cb) required capacitance is 220nf at 2v. suitable component typically 470nf. table 118 charge pump external capacitors ceramic capacitors are recommended for these charge pump requirements. note that, due to the wide tolerance of many types of ceramic capacitors, care must be taken to ensure that the selected components provide the required capacitance across the required temperature and voltage ranges in the intended application. ceramic capacitor s with x5r dielectric are recommended. the positioning of the charge pump capacitors is important, particularly the fly-back capacitors. these capacitors should be placed as close as possible to the WM5102. the component choice and positioning of the cp1 components are more critic al than those of cp2, due to the higher output power requirements of cp1. external accessory detection components the external accessory detection circuit measures jack inserti on using the jackdet pin. the insertion switch status is detected using an inte rnal pull-up resistor circ uit on the jackdet pin. microphone detection and key-button press detection is supported using the micdetn pins. the applicable pin should be connected to one of the micbiasn outputs, via a 2.2k ? current-limiting resistor, as described in the ?mic rophone bias circuit? section. note that, when using the external accessory detection function, the micbiasn resistor must be 2.2k ? +/-2%. a recommended circuit configuration, including headphone output on hpout1 and microphone connections, is shown in figure 86. see ?analogue input paths? for details of the dc-blocking microphone input capacitor selection. the recommended external components and connecti ons for microphone / push-button detection are illustrated in figure 87. note that, when using the microphone detect circ uit, it is recommended to use one of the right channel analogue microphone input paths, to ensure best immunity to electr ical transients arising from the external accessory.
production data WM5102 w pd, may 2013, rev 4.0 303 figure 86 external accessory detection the accessory detection circuit measures the im pedance of an external load connected to one of the micdet pins. the microphone detection circui t uses micvdd, micbias1, micbias2 or micbias3 as a reference. the applicable source is configured using the micd_bias_src register. the WM5102 can detect the presence of a typica l microphone and up to 6 push-buttons, using the components shown in figure 87. when the microphone detection circuit is enabl ed, then each of the push-buttons shown will cause a different bi t within the micd_lvl register to be set. the microphone detect function is specifically des igned to detect a video accessory (typical 75 ? ) load if required. a measured external impedance of 75 ? will cause the micd_lvl [3] bit to be set. figure 87 external accessory detect connection
WM5102 production data w pd, may 2013, rev 4.0 304 recommended external components diagram WM5102 avdd cpvdd cp1ca cp1voutn cp1voutp cp1cb 2.2 f 4.7 f 4.7 f 4.7 f 4.7 f 4.2v 1.8v ldovout spkvddl 4.7 f dbvdd1 dbvdd2 dbvdd3 5 x 0.1 f analogue and digital inputs outputs hpout1 and hpout2 can be configured as stereo pairs or differential mono. spkvddr ldovdd dcvdd 4.7 f vrefc 1.0 f gpio gpio3 gpio4 gpio5 digital speaker (pdm) interface spkclk spkdat hpout1r hpout1fb1/micdet2 hpout1l headphone (note: hpout1fb ground connection close to headset jack) cif1sda cif1sclk control interface 1 cif1addr mclk1 mclk2 master clocks aif1rxdat aif1lrclk aif1bclk aif1txdat audio interface 1 aif2rxdat aif2lrclk aif2bclk aif2txdat audio interface 2 audio interface 3 aif3rxdat aif3lrclk aif3bclk aif3txdat ldoena ldo control reset reset control cp2ca cp2vout cp2cb 470nf 4.7 f spkgndr dgnd cpgnd agnd spkgndl hpout2r hpout2fb hpout2l (note: hpout2fb ground connection close to headset jack) epoutn epoutp earpiece speaker spkoutln spkoutrp spkoutrn spkoutlp loudspeaker loudspeaker hpdetl hpdetr micbias2 micbias1 micbias3 micvdd bias / supplies for microphones and external accessory detection differential microphone connection single-ended line connection stereo digital microphone connection 4.7 f gpio1 gpio2 irq interrupt output slimdat slimclk slimbus interface cif2ss cif2sclk cif2miso cif2mosi control interface 2 jackdet jack detect input in2lp in2ln/dmicclk2 in2rp in2rn/dmicdat2 1 f 1 f in3ln/dmicclk3 in3lp in3rn/dmicdat3 in3rp dmic clk dat clk dat vdd chan micbias2 dmic gnd vdd chan gnd in1lp in1rn/dmicdat1 in1rp in1ln/dmicclk1 1 f micdet1/hpout1fb2 1 f 2.2k 2.2k micbias1 line output
production data WM5102 w pd, may 2013, rev 4.0 305 digital audio interface clocking configurations the digital audio interfaces (aif1, aif2, aif3) c an be configured in master or slave modes. in all applications, it is important that the system clocki ng configuration is correctly designed. incorrect clock configurations will lead to audible clicks arisi ng from dropped or repeated audio samples; this is caused by the inherent tolerances of multiple asynchronous system clocks. to ensure reliable clocking of the audio interface f unctions, it is a requirement that the external interface clocks (eg. bclk, lrclk) are derived from the same clock source as sysclk (or asyncclk, where applicable). in aif master mode, the external bclk and lrclk signals are generated by the WM5102 and synchronisation of these signals with sysclk (or asyncclk) is guaranteed. in this case, clocking of the aif is typically derived from the mclk1 or mc lk2 inputs, either directly or via one of the frequency locked loop (fll) circuits. it is also possible to use a different interface (aifn or slimbus) to provide the reference clock to which the aif master can be synchronised. in aif slave mode, the external bclk and lrcl k signals are generated by another device, as inputs to the WM5102. in this case, it must be ensur ed that the applicable system clock (sysclk or asyncclk) is generated from a source that is sync hronised to the external bclk and lrclk inputs. in a typical slave mode application, the bclk input is selected as the clock reference, using the fll to perform frequency shifting. it is also possible to use the mclk1 or mclk2 inputs, but only if the selected clock is synchronised exte rnally to the bclk and lrclk inputs. the slimbus interface can also provide the clock reference, via one of the flls, provided that the bclk and lrclk signals are externally synchronised with the slimclk input. the valid aif clocking configurations are listed in table 119 for aif master and aif slave modes. the applicable system clock (sysclk or asy ncclk) depends on the aifn_rate setting for the relevant digital audio interface; if aif n_rate < 1000, then sysclk is applicable; if aifn_rate 1000, then asyncclk is applicable. aif mode clocking configuration aif master mode sysclk_src (asyncclk_src) selects mclk1 or mclk2 as sysclk (asyncclk) source. sysclk_src (asyncclk_src) select s flln as sysclk (asyncclk) source; flln_refclk_src selects mc lk1 or mclk2 as flln source. sysclk_src (asyncclk_src) select s flln as sysclk (asyncclk) source; flln_refclk_src selects a different interface (bclk, lrclk, slimclk) as flln source. aif slave mode sysclk_src (asyncclk_src) selects flln as sysclk (asyncclk) source; flln_refclk_src sele cts bclk as flln source. sysclk_src (asyncclk_src) selects mclk1 or mclk2 as sysclk (asyncclk) source, provided mclk is ex ternally synchronised to the bclk input. sysclk_src (asyncclk_src) select s flln as sysclk (asyncclk) source; flln_refclk_src selects mc lk1 or mclk2 as flln source, provided mclk is externally sy nchronised to the bclk input. sysclk_src (asyncclk_src) select s flln as sysclk (asyncclk) source; flln_refclk_src selects a diffe rent interface (eg. slimclk) as flln source, provided the other interfac e is externally synchronised to the bclk input. table 119 audio interface (aif) clocking confgurations
WM5102 production data w pd, may 2013, rev 4.0 306 in each case, the sysclk (asyncclk) frequency must be a valid ratio to the lrclk frequency; the supported clocking rates are defined by the sysclk_freq (async_clk_freq) and sample_rate_n (async_sample_rate_n) registers. the valid aif clocking configurations are illustrated in figure 88 to figure 94 below. note that, where mclk1 is illustrated as the clock source, it is equa lly possible to select mclk2 as the clock source. similarly, in cases where fll1 is illustrat ed, it is equally possible to select fll2. figure 88 aif master mode, using mclk as reference figure 89 aif master mode, using mclk and fll as reference
production data WM5102 w pd, may 2013, rev 4.0 307 figure 90 aif master mode, using another interface as reference WM5102 aifn (slave mode) processor aifnbclk aifnlrclk aifnrxdat aifntxdat fll1_refclk_src fll1 sysclk (or asyncclk) sysclk_src (or asyncclk_src) figure 91 aif slave mode, using bclk and fll as reference
WM5102 production data w pd, may 2013, rev 4.0 308 aifn (slave mode) WM5102 processor aifnbclk aifnlrclk aifnrxdat aifntxdat sysclk (or asyncclk) sysclk_src (or asyncclk_src) synchronous clock generator figure 92 aif slave mode, using mclk as reference figure 93 aif slave mode, using mclk and fll as reference
production data WM5102 w pd, may 2013, rev 4.0 309 figure 94 aif slave mode, using another interface as reference pcb layout considerations poor pcb layout will degrade the performance and be a contributory factor in emi, ground bounce and resistive voltage losses. all external co mponents should be placed as close to the WM5102 device as possible, with current loop areas kept as small as possible.
WM5102 production data w pd, may 2013, rev 4.0 310 package dimensions
production data WM5102 w pd, may 2013, rev 4.0 311 important notice wolfson microelectronics plc (?wol fson?) products and services are sold subject to wolfson?s te rms and conditions of sale, deli very and payment supplied at the time of order acknowledgement. wolfson warrants performance of its products to the specifications in effect at the dat e of shipment. wolfson reserves the righ t to make changes to its products and specificati ons or to discontinue any product or servic e without notice. customers should there fore obtain the latest version of relevant information from wolfson to verify that the information is current. testing and other quality control techniques are utilised to the ex tent wolfson deems necessary to support its warranty. speci fic testing of all parameters of each device is not necessa rily performed unless required by law or regulation. in order to minimise risks associated wi th customer applications, the customer must use adequate design and operating safeguard s to minimise inherent or procedur al hazards. wolfson is not liable for applicati ons assistance or customer product design. the customer is solely responsible for its selection and use of wolf son products. wolfson is not li able for such selection or use nor for use of any circuitry other than circui try entirely embodied in a wolfson product. wolfson?s products are not intended for use in life support system s, appliances, nuclear systems or systems where malfunction c an reasonably be expected to result in personal injury, death or seve re property or environmental damage. any use of products by the customer for such purposes is at the customer?s own risk. wolfson does not grant any licence (express or implied) under any patent right, copyright, mask work right or other intellectua l property right of wolfson covering or relating to any combination, machine, or process in which its products or services might be or are used. any provision or publication of any third party?s products or services does not constitute wo lfson?s approval, licen ce, warranty or endorsement thereof. any third party trade marks contained in this document belong to the respective third party o wner. reproduction of information from wolfson datasheets is permissible only if reproduction is without alteration and is accompanie d by all associated copyright, proprietary and ot her notices (including this notice) and conditions. wo lfson is not liable for any unauthorised alteration of such information or for any reliance placed thereon. any representations made, warranties given, and/or liabilities accepted by any person which differ from those contained in this datasheet or in wolfson?s standard terms and conditions of sale, delivery and payment are made, given and/or accepted at that person?s own risk. wolfson is not liable for any such represent ations, warranties or liabilities or for any reliance placed the reon by any person. address: wolfson microelectronics plc 26 westfield road edinburgh eh11 2qb united kingdom tel :: +44 (0)131 272 7000 fax :: +44 (0)131 272 7001 email :: sales@wolfsonmicro.com
WM5102 production data w pd, may 2013, rev 4.0 312 revision history date rev description of changes page changed by 05/04/12 1.0 initial version ph 18/04/12 2.0 hpdet_sts, micdet_sts deleted pwm_clk_sel description updated (50mhz option deleted). ph 08/06/12 2.0 sample rates greater than 192khz deleted. power domain information added. dcvdd & configuration requirements for 50mhz clocking added. electrical characteristics updated (min/max limits deleted). fll synchroniser timing requirements added. dmicclk, spkclk, bclk timing requirements updated. lra_freq register description updated (haptics). added details of the supported sample rates for different blocks. additional details of slimbus clocking & framer functions. output path noise gate function added. eci_jd_src register deleted. eci_bias_src register updated, noti ng permitted configurations of eci digital/analogue bias sources. ldo2_ena and ldo2_bypass register deleted ? these are slaved to the cp2 controls. clocking configuration applicati ons info updated to incorporate slimbus interface options. analogue connections updated on ex ternal components figure. ph 03/07/12 2.0 update to gpio fll clock output: flln_gpclk_div controls the frequency relative to fvco, ie. independent of flln_outdiv. volume ramp register descriptions updated. maximum ldo2 output voltage amended to 3.25v. ph 30/07/12 2.0 drc2 deleted hp_clk_div register deleted gp_dbtime register updated dsp firmware memory definitions updated micbias description moved to charge pump & regulator section. ph 05/10/12 2.0 package drawing updated. input pin descriptions corrected. subsys_max_freq bit, and associated ldo requirements added, enabling 49.152mhz dsp clocking.. noted left-justified and dsp-b modes valid in master mode only. maximum ldo2 output voltage reverted to 3.3v. electrical characteristics updated. noted micvdd required for analogue inputs. changed descriptions of input pga & output pga ramp control registers. typical aif system connections updated. noted aif format is 2?s complement. noted lrclk rate registers only applicable in slave mode. noted micvdd required for accessory detection. deleted 64khz & 128khz audio sample rates. noted 32khz clock required for cp2. ph 15/10/12 2.0 rev b silicon updates added: support for second asyncclk sample rate. write sequencer trigger functi on from drc signal detect added. enhancement to headphone impedance measurement. added micdet clamp and associated wkup/wseq controls. input pin maximum ratings updated; recommended to use righ t channel analogue mic paths when using accessory detect. ph
production data WM5102 w pd, may 2013, rev 4.0 313 date rev description of changes page changed by 18/10/12 2.0 package drawing updated. i2c timing diagram updated, with additional ?sda valid? parameter. ph 13/11/12 2.0 electrical characteristics updated. out[1-4]_osr register bits deleted. outnx_pga_vol registers deleted. correction to pin numbering (spkoutlp, spkoutln, spkoutrp, spkoutrn) ph 14/12/12 3.0 updates describing automatic gain in aec loopback path. package drawing updated. generic description added for digital core mixer control registers. typical power consumption data added ph 19/02/13 3.0 electrical characteristics updated. esd diode configuration details added for external outputs. out4_osr register bit reinstated. ph 20/03/13 4.0 fll gain and bandwidth control registers added. dsp firmware memory rese t conditions am ended (including dsp1_mem_ena description). dma register control requirements added for disabling dsp. ph 08/05/13 4.0 deleted statements about automatic thermal shutdown - speaker drivers must be disabled via software control. im_boot_done_eint2 updated (default is 0 - unmasked) ph

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